Icestorm: LDP (signed offset, 64-bit) measurements

Code:

  ldp x0, x1, [x6, #8]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
2005	846	1031	1	1030	1000	5188	1000	2000	2000	1	1000	1000
2004	543	1001	1	1000	1000	5188	1000	2000	2000	1	1000	1000
2004	543	1001	1	1000	1000	5188	1000	2000	2000	1	1000	1000
2004	543	1001	1	1000	1000	5188	1000	2000	2000	1	1000	1000
2004	543	1001	1	1000	1000	5188	1000	2000	2000	1	1000	1000
2004	543	1001	1	1000	1000	5188	1000	2000	2000	1	1000	1000
2004	543	1001	1	1000	1000	5188	1000	2000	2000	1	1000	1000
2004	543	1001	1	1000	1000	5188	1000	2000	2000	1	1000	1000
2004	543	1001	1	1000	1000	5188	1000	2000	2000	1	1000	1000
2004	543	1001	1	1000	1000	5188	1000	2000	2000	1	1000	1000

Test 2: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldp x0, x1, [x6, #8]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50205	70156	40108	30107	10001	30130	10003	1855835	709975	40106	30212	20008	60224	20008	30003	10000	40100
50204	70049	40103	30103	10000	30103	10003	1858397	710995	40106	30212	20008	60224	20008	30002	10000	40100
50204	70054	40103	30103	10000	30103	10003	1858370	710981	40106	30212	20008	60224	20008	30002	10000	40100
50204	70042	40102	30102	10000	30103	10003	1858343	710971	40106	30212	20008	60224	20008	30002	10000	40100
50204	70042	40102	30102	10000	30103	10003	1858343	710971	40106	30212	20008	60224	20008	30002	10000	40100
50204	70042	40102	30102	10000	30103	10003	1858343	710971	40106	30212	20008	60224	20008	30002	10000	40100
50204	70042	40102	30102	10000	30103	10003	1858343	710971	40106	30212	20008	60224	20008	30002	10000	40100
50204	70042	40102	30102	10000	30103	10003	1858343	710971	40106	30212	20008	60224	20008	30002	10000	40100
50204	70042	40102	30102	10000	30103	10003	1858343	710971	40106	30212	20008	60224	20008	30002	10000	40100
50204	70042	40102	30102	10000	30103	10003	1858343	710971	40106	30212	20008	60298	20035	30008	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0041

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50025	70156	40018	30017	10001	30040	10003	1858779	711946	40016	30032	20008	60020	20000	30002	10000	40010
50024	70047	40013	30013	10000	30010	10000	1858760	711905	40010	30020	20000	60020	20000	30002	10000	40010
50024	70040	40012	30012	10000	30010	10000	1858760	711905	40010	30020	20000	60020	20000	30002	10000	40010
50024	70040	40012	30012	10000	30010	10000	1858760	711905	40010	30020	20000	60020	20000	30002	10000	40010
50024	70040	40012	30012	10000	30010	10015	1859413	712132	40060	30070	20034	60020	20000	30002	10000	40010
50024	70040	40012	30012	10000	30010	10000	1858760	711905	40010	30020	20000	60020	20000	30002	10000	40010
50024	70040	40012	30012	10000	30010	10000	1858760	711905	40010	30020	20000	60020	20000	30002	10000	40010
50024	70040	40012	30012	10000	30010	10000	1858760	711905	40010	30020	20000	60020	20000	30002	10000	40010
50024	70040	40012	30012	10000	30010	10000	1858760	711905	40010	30020	20000	60020	20000	30002	10000	40010
50024	70040	40012	30012	10000	30010	10000	1858787	711917	40010	30020	20000	60020	20000	30002	10000	40010

Test 3: Latency 2->3 (with chain penalty)

Chain cycles: 3

Code:

  ldp x0, x1, [x6, #8]
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50205	70150	40108	30107	10001	30130	10003	1857764	710818	40106	30212	20008	60224	20008	30003	10000	40100
50204	70049	40103	30103	10000	30103	10003	1858532	711041	40106	30212	20008	60224	20008	30003	10000	40100
50204	70049	40103	30103	10000	30103	10003	1858532	711041	40106	30212	20008	60224	20008	30003	10000	40100
50204	70049	40103	30103	10000	30103	10003	1858532	711041	40106	30212	20008	60224	20008	30003	10000	40100
50204	70049	40103	30103	10000	30103	10003	1858532	711041	40106	30212	20008	60224	20008	30003	10000	40100
50204	70049	40103	30103	10000	30103	10003	1858532	711041	40106	30212	20008	60224	20008	30003	10000	40100
50204	70049	40103	30103	10000	30103	10015	1858870	711168	40152	30250	20034	60224	20008	30003	10000	40100
50204	70049	40103	30103	10000	30103	10003	1858532	711041	40106	30212	20008	60224	20008	30003	10000	40100
50204	70049	40103	30103	10000	30103	10003	1858532	711041	40106	30212	20008	60224	20008	30003	10000	40100
50204	70049	40103	30103	10000	30103	10003	1858532	711041	40106	30212	20008	60224	20008	30003	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50025	70166	40018	30017	10001	30040	10003	1858833	711966	40016	30032	20008	60020	20000	30002	10000	40010
50024	70042	40012	30012	10000	30010	10000	1858814	711925	40010	30020	20000	60020	20000	30002	10000	40010
50024	70045	40012	30012	10000	30010	10000	1858814	711925	40010	30020	20000	60020	20000	30002	10000	40010
50024	70042	40012	30012	10000	30010	10000	1858841	711936	40010	30020	20000	60020	20000	30002	10000	40010
50024	70042	40012	30012	10000	30010	10000	1858868	711947	40010	30020	20000	60020	20000	30002	10000	40010
50024	70042	40012	30012	10000	30010	10000	1858814	711925	40010	30020	20000	60020	20000	30002	10000	40010
50024	70042	40012	30012	10000	30010	10000	1858814	711925	40010	30020	20000	60020	20000	30002	10000	40010
50024	70042	40012	30012	10000	30010	10000	1858814	711925	40010	30020	20000	60020	20000	30002	10000	40010
50024	70042	40012	30012	10000	30010	10000	1858841	711936	40010	30020	20000	60020	20000	30002	10000	40010
50024	70049	40012	30012	10000	30010	10000	1858895	711958	40010	30020	20000	60020	20000	30002	10000	40010

Test 4: throughput

Count: 8

Code:

  ldp x0, x1, [x6, #8]
  ldp x0, x1, [x6, #8]
  ldp x0, x1, [x6, #8]
  ldp x0, x1, [x6, #8]
  ldp x0, x1, [x6, #8]
  ldp x0, x1, [x6, #8]
  ldp x0, x1, [x6, #8]
  ldp x0, x1, [x6, #8]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5013

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160205	40261	80134	101	80033	100	80012	300	242894	80112	200	160024	200	160024	1	80000	80100
160204	40107	80109	101	80008	100	80012	300	296089	80112	200	160024	200	160024	1	80000	80100
160204	40105	80109	101	80008	100	80012	300	270782	80112	200	160024	200	160024	1	80000	80100
160204	40105	80109	101	80008	100	80012	300	254726	80112	200	160024	200	160024	1	80000	80100
160204	40105	80109	101	80008	100	80012	300	254726	80112	200	160024	200	160024	1	80000	80100
160204	40105	80109	101	80008	100	80012	300	254726	80112	200	160024	200	160024	1	80000	80100
160204	40105	80109	101	80008	100	80012	300	254726	80112	200	160024	200	160024	1	80000	80100
160204	40105	80109	101	80008	100	80012	300	254726	80112	200	160024	200	160024	1	80000	80100
160204	40105	80109	101	80008	100	80012	300	254726	80112	200	160024	200	160024	1	80000	80100
160204	40105	80109	101	80008	100	80012	300	254726	80112	200	160024	200	160024	1	80000	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160025	40521	80043	11	80032	10	80056	30	318805	80066	20	160112	20	160000	1	80000	80010
160024	40078	80011	11	80000	10	80000	30	243466	80010	20	160000	20	160000	1	80000	80010
160024	40057	80011	11	80000	10	80000	30	243466	80010	20	160000	20	160000	1	80000	80010
160024	40059	80011	11	80000	10	80000	30	243466	80010	20	160000	20	160000	1	80000	80010
160024	40057	80011	11	80000	10	80000	30	243466	80010	20	160000	20	160000	1	80000	80010
160024	40057	80011	11	80000	10	80000	30	243466	80010	20	160000	20	160000	1	80000	80010
160024	40057	80011	11	80000	10	80000	30	243466	80010	20	160000	20	160000	1	80000	80010
160024	40057	80011	11	80000	10	80000	30	243466	80010	20	160000	20	160000	1	80000	80010
160025	40115	80041	11	80030	10	80000	30	472712	80010	20	160000	20	160000	1	80000	80010
160024	40062	80011	11	80000	10	80000	30	314560	80010	20	160000	20	160000	1	80000	80010

LDP (signed offset, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations