Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

STLLRH

Test 1: uops

Code:

  stllrh w0, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	6338	1019	1	1018	1000	104694	1000	1000	2000	1	1000
1004	6063	1001	1	1000	1000	104694	1000	1000	2000	1	1000
1004	6063	1001	1	1000	1000	104694	1000	1000	2000	1	1000
1004	6063	1001	1	1000	1000	104694	1000	1000	2000	1	1000
1004	6063	1001	1	1000	1000	104730	1000	1000	2000	1	1000
1004	6063	1001	1	1000	1000	104694	1000	1000	2000	1	1000
1004	6063	1001	1	1000	1000	104694	1000	1000	2000	1	1000
1004	6063	1001	1	1000	1000	104694	1000	1000	2000	1	1000
1004	6063	1001	1	1000	1000	104694	1000	1000	2000	1	1000
1004	6063	1001	1	1000	1000	104694	1000	1000	2000	1	1000

Test 2: throughput

Code:

  stllrh w0, [x6]
  add x6, x6, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 6.0079

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
20206	60316	20212	10176	0	10036	10175	0	10000	35662	1068094	0	20101	10203	10003	0	10203	20006	10002	10000	0	10100
20204	60083	20102	10102	0	10000	10101	0	10000	35658	1067968	0	20100	10202	10002	0	10202	20004	10001	10000	0	10100
20204	60076	20101	10101	0	10000	10100	0	10000	35658	1067968	0	20100	10202	10002	0	10202	20004	10001	10000	0	10100
20204	60076	20101	10101	0	10000	10100	0	10000	35658	1067968	0	20100	10202	10002	0	10233	20068	10032	10000	0	10100
20204	60076	20101	10101	0	10000	10100	0	10000	35658	1067968	0	20100	10202	10002	0	10202	20004	10001	10000	0	10100
20204	60076	20101	10101	0	10000	10100	0	10000	35658	1067968	0	20100	10202	10002	0	10202	20004	10001	10000	0	10100
20205	60150	20151	10133	0	10018	10132	0	10000	35658	1068220	0	20100	10202	10002	0	10202	20004	10001	10000	0	10100
20204	60076	20101	10101	0	10000	10100	0	10000	35658	1067968	0	20100	10202	10002	0	10202	20004	10001	10000	0	10100
20204	60077	20101	10101	0	10000	10100	0	10000	35658	1067968	0	20100	10202	10002	0	10202	20004	10001	10000	0	10100
20204	60076	20101	10101	0	10000	10100	0	12338	85742	1093456	316	25307	14212	12796	23	5365	9095	4599	4496	3	4730

1000 unrolls and 10 iterations

Result (median cycles for code): 6.0079

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20026	60371	20120	10084	10036	10083	10000	35433	1068094	20010	10022	10002	10020	20000	10001	10000	10010
20024	60083	20011	10011	10000	10010	10000	35433	1068094	20010	10020	10000	10020	20000	10001	10000	10010
20024	60083	20011	10011	10000	10010	10000	35433	1068094	20010	10020	10000	10020	20000	10001	10000	10010
20024	60083	20011	10011	10000	10010	10000	35433	1068094	20010	10020	10000	10020	20000	10001	10000	10010
20024	60083	20011	10011	10000	10010	10000	35433	1068670	20010	10020	10000	10020	20000	10001	10000	10010
20024	60083	20011	10011	10000	10010	10000	35433	1068094	20010	10020	10000	10020	20000	10001	10000	10010
20024	60083	20011	10011	10000	10010	10000	35433	1068094	20010	10020	10000	10020	20000	10001	10000	10010
20024	60083	20011	10011	10000	10010	10000	35433	1068346	20010	10020	10000	10020	20000	10001	10000	10010
20024	60083	20011	10011	10000	10010	10000	35433	1068094	20010	10020	10000	10020	20000	10001	10000	10010
20024	60083	20011	10011	10000	10010	10000	35433	1068094	20010	10020	10000	10020	20000	10001	10000	10010

Test 3: throughput

Code:

  stllrh w0, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 6.0056

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10206	60188	10139	103	10036	102	10000	300	1067694	10100	200	10004	200	20008	0	1	10000	0	100
10204	60063	10101	101	10000	100	10000	300	1067552	10100	200	10004	200	20008	0	1	10000	0	100
10204	60056	10101	101	10000	100	10000	300	1067552	10100	200	10004	200	20008	0	1	10000	0	100
10204	60056	10101	101	10000	100	10000	300	1067552	10100	200	10004	200	20008	0	1	10000	0	100
10204	60056	10101	101	10000	100	10000	300	1067552	10100	200	10004	3300	22787	52	1593	11298	32	2287
10204	60057	10101	101	10000	100	10000	300	1067552	10100	200	10004	200	20008	0	1	10000	0	100
10204	60056	10101	101	10000	100	10000	300	1067552	10100	200	10004	200	20008	0	1	10000	0	100
10204	60056	10101	101	10000	100	10000	300	1067552	10100	200	10004	200	20008	0	1	10000	0	100
10204	60056	10101	101	10000	100	10000	300	1067552	10100	200	10004	200	20008	0	1	10000	0	100
10204	60056	10101	101	10000	100	10000	300	1067552	10100	200	10004	200	20008	0	1	10000	0	100

1000 unrolls and 10 iterations

Result (median cycles for code): 6.0058

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10024	60113	10011	11	0	10000	10	0	10000	30	1067588	0	10010	20	10000	0	20	20104	0	1	10000	0	10
10024	60065	10011	11	0	10000	10	0	10000	30	1067588	0	10010	20	10000	0	20	20000	0	1	10000	0	10
10024	60058	10011	11	0	10000	10	0	10000	30	1067588	0	10010	20	10000	0	20	20000	0	1	10000	0	10
10024	60058	10011	11	0	10000	10	0	10000	30	1067588	0	10010	20	10000	0	20	20000	0	1	10000	0	10
10024	60058	10011	11	0	10000	10	0	10000	30	1067588	0	10010	20	10000	0	20	20000	0	1	10000	0	10
10024	60058	10011	11	0	10000	10	0	10000	30	1067588	0	10010	20	10000	0	20	20000	0	1	10000	0	10
10024	60058	10011	11	0	10000	10	0	10000	30	1067588	0	10010	20	10000	0	20	20000	0	1	10000	0	10
10024	60058	10011	11	0	10000	10	0	10000	30	1067588	0	10010	20	10000	0	20	20000	0	1	10000	0	10
10024	60058	10011	11	0	10000	10	0	10000	30	1067588	0	10010	20	10000	0	20	20000	0	1	10000	0	10
10024	60058	10011	11	0	10000	10	0	10000	30	1067588	0	10010	20	10000	0	20	20104	0	1	10000	0	10