Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

PRFM (register, PSTL2KEEP)

Test 1: uops

Code:

  prfm pstl2keep, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1004	2066	1001	1	1000	1000	34126	1000	1000	1000	1	1000
1004	2051	1001	1	1000	1000	34126	1000	1000	1000	1	1000
1004	2051	1001	1	1000	1000	34126	1000	1000	1000	1	1000
1004	2051	1001	1	1000	1000	34126	1000	1000	1000	1	1000
1004	2051	1001	1	1000	1000	34126	1000	1000	1000	1	1000
1004	2051	1001	1	1000	1000	34126	1000	1000	1000	1	1000
1004	2051	1001	1	1000	1000	34126	1000	1000	1000	1	1000
1004	2051	1001	1	1000	1000	34126	1000	1000	1000	1	1000
1004	2051	1001	1	1000	1000	34126	1000	1000	1000	1	1000
1004	2051	1001	1	1000	1000	34126	1000	1000	1000	1	1000

Test 2: throughput

Code:

  prfm pstl2keep, [x6]
  add x6, x6, 64

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0082

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20204	21085	20106	10106	10000	10111	10006	61227	349431	0	20117	10213	10013	0	10213	10013	10006	10000	10100
20204	20056	20106	10106	10000	10111	10006	61293	349457	0	20118	10214	10014	0	10214	10014	10006	10000	10100
20204	20056	20106	10106	10000	10112	10006	61293	349457	0	20118	10214	10014	0	10214	10014	10006	10000	10100
20204	20056	20106	10106	10000	10112	10006	61293	349457	0	20118	10214	10014	0	10214	10014	10006	10000	10100
20204	20056	20106	10106	10000	10112	10039	62046	348838	0	20183	10246	10046	0	10214	10014	10006	10000	10100
20204	20056	20106	10106	10000	10112	10006	61293	349457	0	20118	10214	10014	0	10214	10014	10006	10000	10100
20204	20056	20106	10106	10000	10112	10006	61293	349457	0	20118	10214	10014	0	10214	10014	10006	10000	10100
20204	20056	20106	10106	10000	10112	10006	61293	349457	0	20118	10214	10014	0	10214	10014	10006	10000	10100
20204	20056	20106	10106	10000	10112	10006	61293	349457	0	20118	10214	10014	0	10214	10014	10006	10000	10100
20204	20056	20106	10106	10000	10112	10006	61293	349457	0	20118	10214	10014	0	10214	10014	10006	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0065

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20024	20490	20013	10013	10000	10017	10000	60543	349009	20010	10020	10000	10020	10000	10001	10000	10010
20024	20031	20011	10011	10000	10010	10000	61079	349953	20010	10020	10000	10020	10000	10001	10000	10010
20024	20036	20011	10011	10000	10010	10000	61068	349623	20010	10020	10000	10020	10000	10001	10000	10010
20024	20044	20011	10011	10000	10010	10000	61013	350841	20010	10020	10000	10020	10000	10001	10000	10010
20024	20148	20011	10011	10000	10010	10000	60675	349197	20010	10020	10000	10020	10000	10001	10000	10010
20024	20058	20011	10011	10000	10010	10000	61025	348259	20010	10020	10000	10020	10000	10001	10000	10010
20024	20076	20011	10011	10000	10010	10000	61274	348679	20010	10020	10000	10020	10000	10001	10000	10010
20024	20019	20011	10011	10000	10010	10000	60744	351327	20010	10020	10000	10020	10000	10001	10000	10010
20024	20048	20011	10011	10000	10010	10000	61252	349417	20010	10020	10000	10020	10000	10001	10000	10010
20024	20065	20011	10011	10000	10010	10000	60876	350027	20010	10020	10000	10020	10000	10001	10000	10010

Test 3: throughput

Code:

  prfm pstl2keep, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0503

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10204	20960	10101	101	10000	100	10006	300	357314	10106	200	10014	200	10012	1	10000	100
10204	20503	10101	101	10000	100	10006	300	357338	10106	200	10012	200	10012	1	10000	100
10204	20503	10101	101	10000	100	10006	300	357346	10106	200	10012	200	10012	1	10000	100
10204	20503	10101	101	10000	100	10006	300	357346	10106	200	10012	200	10012	1	10000	100
10204	20503	10101	101	10000	100	10006	300	357346	10106	200	10012	200	10012	1	10000	100
10204	20503	10101	101	10000	100	10006	300	357346	10106	200	10012	200	10012	1	10000	100
10204	20521	10101	101	10000	100	10000	300	357182	10100	200	10004	200	10008	1	10000	100
10204	20522	10101	101	10000	100	10002	300	357316	10102	200	10012	200	10012	1	10000	100
10204	20490	10101	101	10000	100	10000	300	356156	10100	200	10004	200	10012	1	10000	100
10204	20503	10101	101	10000	100	10006	300	357346	10106	200	10012	200	10012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0958

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10024	20959	10011	11	10000	10	10006	30	365438	10016	20	10012	20	10000	1	10000	10
10024	20958	10011	11	10000	10	10000	30	365426	10010	20	10000	20	10000	1	10000	10
10024	20958	10011	11	10000	10	10000	30	365426	10010	20	10000	20	10000	1	10000	10
10024	20958	10011	11	10000	10	10000	30	365426	10010	20	10000	20	10000	1	10000	10
10024	20872	10011	11	10000	10	10000	30	363006	10010	20	10000	20	10228	1	10000	10
10024	20569	10011	11	10000	10	10000	30	361748	10010	20	10000	20	10000	1	10000	10
10024	20810	10011	11	10000	10	10048	30	362637	10058	20	10057	20	10000	1	10000	10
10024	20835	10011	11	10000	10	10000	30	363864	10010	20	10000	20	10000	1	10000	10
10024	20958	10011	11	10000	10	10000	30	365426	10010	20	10000	20	10057	1	10000	10
10024	20961	10011	11	10000	10	10000	30	365330	10010	20	10000	20	10000	1	10000	10