Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

PRFM (register, PSTL2KEEP)

Test 1: uops

Code:

  prfm pstl2keep, [x6]
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
1004206610011100010003412610001000100011000
1004205110011100010003412610001000100011000
1004205110011100010003412610001000100011000
1004205110011100010003412610001000100011000
1004205110011100010003412610001000100011000
1004205110011100010003412610001000100011000
1004205110011100010003412610001000100011000
1004205110011100010003412610001000100011000
1004205110011100010003412610001000100011000
1004205110011100010003412610001000100011000

Test 2: throughput

Code:

  prfm pstl2keep, [x6]
  add x6, x6, 64

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0082

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
2020421085201061010610000101111000661227349431020117102131001301021310013100061000010100
2020420056201061010610000101111000661293349457020118102141001401021410014100061000010100
2020420056201061010610000101121000661293349457020118102141001401021410014100061000010100
2020420056201061010610000101121000661293349457020118102141001401021410014100061000010100
2020420056201061010610000101121003962046348838020183102461004601021410014100061000010100
2020420056201061010610000101121000661293349457020118102141001401021410014100061000010100
2020420056201061010610000101121000661293349457020118102141001401021410014100061000010100
2020420056201061010610000101121000661293349457020118102141001401021410014100061000010100
2020420056201061010610000101121000661293349457020118102141001401021410014100061000010100
2020420056201061010610000101121000661293349457020118102141001401021410014100061000010100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0065

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
20024204902001310013100001001710000605433490092001010020100001002010000100011000010010
20024200312001110011100001001010000610793499532001010020100001002010000100011000010010
20024200362001110011100001001010000610683496232001010020100001002010000100011000010010
20024200442001110011100001001010000610133508412001010020100001002010000100011000010010
20024201482001110011100001001010000606753491972001010020100001002010000100011000010010
20024200582001110011100001001010000610253482592001010020100001002010000100011000010010
20024200762001110011100001001010000612743486792001010020100001002010000100011000010010
20024200192001110011100001001010000607443513272001010020100001002010000100011000010010
20024200482001110011100001001010000612523494172001010020100001002010000100011000010010
20024200652001110011100001001010000608763500272001010020100001002010000100011000010010

Test 3: throughput

Code:

  prfm pstl2keep, [x6]
  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0503

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
1020420960101011011000010010006300357314101062001001420010012110000100
1020420503101011011000010010006300357338101062001001220010012110000100
1020420503101011011000010010006300357346101062001001220010012110000100
1020420503101011011000010010006300357346101062001001220010012110000100
1020420503101011011000010010006300357346101062001001220010012110000100
1020420503101011011000010010006300357346101062001001220010012110000100
1020420521101011011000010010000300357182101002001000420010008110000100
1020420522101011011000010010002300357316101022001001220010012110000100
1020420490101011011000010010000300356156101002001000420010012110000100
1020420503101011011000010010006300357346101062001001220010012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0958

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
1002420959100111110000101000630365438100162010012201000011000010
1002420958100111110000101000030365426100102010000201000011000010
1002420958100111110000101000030365426100102010000201000011000010
1002420958100111110000101000030365426100102010000201000011000010
1002420872100111110000101000030363006100102010000201022811000010
1002420569100111110000101000030361748100102010000201000011000010
1002420810100111110000101004830362637100582010057201000011000010
1002420835100111110000101000030363864100102010000201000011000010
1002420958100111110000101000030365426100102010000201005711000010
1002420961100111110000101000030365330100102010000201000011000010