Icestorm: LDRSB (register, sxtw, 64-bit) measurements

Code:

  ldrsb x0, [x6, w7, sxtw]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1004	601	1001	1	1000	1000	8112	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	8130	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8130	1000	1000	2000	1	1000
1004	549	1001	1	1000	1000	8112	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	8148	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	2000	1	1000
1004	549	1001	1	1000	1000	8112	1000	1000	2000	1	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsb x0, [x6, w7, sxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0052

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70294	40108	30107	10001	30130	10003	1859782	693986	40106	30210	10004	60220	20008	30003	10000	30100
40204	70058	40103	30103	10000	30103	10015	1862788	695353	40150	30248	10016	60224	20008	30002	10000	30100
40204	70051	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	30100
40204	70051	40102	30102	10000	30103	10003	1859689	694103	40106	30212	10004	60224	20008	30002	10000	30100
40204	70051	40102	30102	10000	30103	10003	1859689	694103	40106	30212	10004	60224	20008	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859689	694103	40106	30212	10004	60224	20008	30002	10000	30100
40204	70059	40102	30102	10000	30103	10003	1859905	694191	40106	30212	10004	60224	20008	30002	10000	30100
40204	70051	40102	30102	10000	30103	10015	1861222	694708	40150	30251	10017	60224	20008	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859689	694103	40106	30212	10004	60224	20008	30002	10000	30100
40205	70088	40111	30109	10002	30135	10003	1859689	694103	40106	30212	10004	60224	20008	30002	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70156	40018	30017	10001	30040	10000	1859604	693654	40010	30020	10000	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	20000	30003	10000	30010
40025	70077	40021	30019	10002	30045	10000	1860462	695044	40010	30020	10000	60020	20000	30003	10000	30010
40024	70051	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	20000	30003	10000	30010
40024	70052	40013	30013	10000	30010	10015	1860421	694598	40060	30067	10017	60020	20000	30003	10000	30010
40024	70048	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	20000	30003	10000	30010

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrsb x0, [x6, w7, sxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40204	70053	40103	30103	10000	30103	10003	1859539	693896	40106	30210	10004	60220	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1861849	694985	40106	30212	10004	60224	20008	30003	10000	30100
40204	70055	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70255	40018	30017	10001	30040	10052	1866509	698465	40194	30175	10052	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010
40024	70046	40012	30012	10000	30010	10053	1866366	724903	40195	30174	10053	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10016	1859840	714087	40061	30071	10018	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010

Test 4: throughput

Count: 8

Code:

  ldrsb x0, [x6, w7, sxtw]
  ldrsb x0, [x6, w7, sxtw]
  ldrsb x0, [x6, w7, sxtw]
  ldrsb x0, [x6, w7, sxtw]
  ldrsb x0, [x6, w7, sxtw]
  ldrsb x0, [x6, w7, sxtw]
  ldrsb x0, [x6, w7, sxtw]
  ldrsb x0, [x6, w7, sxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40177	80133	101	80032	100	80010	300	640208	80110	200	80014	200	160024	1	80000	100
80204	40059	80105	101	80004	100	80008	300	328190	80108	200	80012	200	160024	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640196	80108	200	80012	200	160024	1	80000	100
80204	40052	80101	101	80000	100	80010	300	640208	80110	200	80014	200	160024	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640196	80108	200	80012	200	160024	1	80000	100
80205	40111	80131	101	80030	100	80008	300	641582	80108	200	80012	200	160024	1	80000	100
80204	40052	80101	101	80000	100	80010	300	640208	80110	200	80014	200	160024	1	80000	100
80204	40061	80101	101	80000	100	80008	300	640340	80108	200	80012	200	160024	1	80000	100
80204	40065	80101	101	80000	100	80008	300	640196	80108	200	80012	200	160024	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640196	80108	200	80012	200	160024	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40244	80043	11	80032	10	80008	30	400262	80018	20	80012	20	160028	1	80000	10
80024	40057	80011	11	80000	10	80057	30	310725	80067	20	80069	20	160028	1	80000	10
80024	40057	80011	11	80000	10	80010	30	640280	80020	20	80014	20	160028	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640238	80010	20	80000	20	160000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640238	80010	20	80000	20	160000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640238	80010	20	80000	20	160000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640238	80010	20	80000	20	160000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640238	80010	20	80000	20	160000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640238	80010	20	80000	20	160000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640238	80010	20	80000	20	160000	1	80000	10

LDRSB (register, sxtw, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations