Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LSR (register, 64-bit)

Test 1: uops

Code:

  lsr x0, x0, x1
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
100410301001100110002560310001000200010011000
100410301001100110002560310001000200010011000
100410301001100110002560310001000200010011000
100410301001100110002560310001000200010011000
100410301001100110002560310001000200010011000
100410301001100110002560310001000200010011000
100410301001100110002560310001000200010011000
100410301001100110002560310001000200010011000
100410301001100110002560310001000200010011000
100410301001100110002560310001000200010011000

Test 2: Latency 1->2

Code:

  lsr x0, x0, x1
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204100301010110101101072593111010710214202281000110100
10204100301010110101101072595391010710212202241000110100
10204100301010110101101072595391010710212202241000110100
10204100301010110101101072595391010710212202241000110100
10204100301010110101101072595391010710212202241000110100
10204100301010110101101072595391010710212202241000110100
10204100301010110101101072595391010710212202241000110100
10204100301010110101101072595391010710212202241000110100
10204100301010110101101072595391010710212202241000110100
10204100301010110101101072595391010710212202241000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024100301002110021100282594901002810034200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010

Test 3: Latency 1->3

Code:

  lsr x0, x1, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204100301010110101101082593301010710214202281000110100
10204100301010110101101072595391010710212202241000110100
10204100301010110101101072595391010710212202241000110100
10204100301010110101101072595391010710212202241000110100
10204100301010110101101072595391010710212202241000110100
10204100301010110101101072595391010710212202241000110100
10204100301010110101101072595391010710212202241000110100
10204100301010110101101072595391010710212202241000110100
10204100301010110101101072595391010710212202241000110100
10204100301010110101101072595391010710212202241000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024100301002110021100282595281003010038200481001110010
10024100301002110021100282596281002810036200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010

Test 4: throughput

Count: 8

Code:

  lsr x0, x8, x9
  lsr x1, x8, x9
  lsr x2, x8, x9
  lsr x3, x8, x9
  lsr x4, x8, x9
  lsr x5, x8, x9
  lsr x6, x8, x9
  lsr x7, x8, x9
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
802042687980115801158012024036080120802221602448001580100
802042674080114801148011924035780119802211602428001580100
802042673780115801158012024036080120802241602428001480100
802052676680157801578017124050480171802731602488001580100
802042673780115801158012024036080120802241602488001580100
802042673780115801158012024036080120802241602488001580100
802042673780115801158012024036080120802241602488001580100
802042673780115801158012024036080120802241602488001580100
802042673780115801158012024036080120802241602488001580100
802042673780115801158012024036080120802241602488001580100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3340

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
800242812780039800398004426406880020800201600208001180010
800242677280021800218002028273880020800201600208001180010
800242671780021800218002028273880020800201600208001180010
800242671780021800218002028273880020800201600208001180010
800242671780021800218002028273880020800201600208001180010
800242671780021800218002028273880020800201600208001180010
800242671780021800218002028273880020800201600208001180010
800242671780021800218002028273880020800201600208001180010
800242671780021800218002028273880020800201600208001180010
800242671780021800218002028273880020800201600208001180010