Icestorm: LDRSH (register, sxtw, 32-bit) measurements

Code:

  ldrsh w0, [x6, w7, sxtw]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	664	1027	1	1026	1000	8238	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	8238	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	2000	1	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh w0, [x6, w7, sxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70150	40108	30107	10001	30130	10003	1859539	693896	40106	30210	10004	60298	20034	30009	10000	30100
40204	70049	40103	30103	10000	30103	10015	1862079	695534	40152	30251	10017	60224	20008	30003	10000	30100
40205	70189	40111	30109	10002	30135	10016	1859903	702950	40151	30249	10018	60302	20034	30009	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40026	70188	40026	30023	10003	30072	10003	1859623	693696	40016	30030	10004	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	20000	30003	10000	30010
40024	70052	40013	30013	10000	30010	10000	1859706	694736	40010	30020	10000	60020	20000	30003	10000	30010
40025	70156	40021	30019	10002	30045	10000	1859922	694824	40010	30020	10000	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859733	694747	40010	30020	10000	60020	20000	30003	10000	30010
40024	70173	40013	30013	10000	30010	10000	1859841	694791	40010	30020	10000	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	20000	30003	10000	30010

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh w0, [x6, w7, sxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
40205	70147	40108	30107	10001	30130	10003	1859296	693806	40106	30210	10004	60220	20008	30002	10000	0	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60302	20034	30008	10000	0	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	0	30100
40205	70134	40110	30108	10002	30135	10003	1859500	694036	40106	30212	10004	60224	20008	30002	10000	0	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	0	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	0	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	0	30100
40204	70040	40102	30102	10000	30103	10016	1861252	722311	40151	30251	10018	61676	21067	30647	10596	3	31030
40204	70042	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	0	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	0	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0060

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70159	40018	30017	10001	30040	10003	1859677	693716	40016	30030	10004	60020	20000	30003	10000	30010
40024	70055	40013	30013	10000	30010	10000	1860057	694877	40010	30020	10000	60020	20000	30003	10000	30010
40024	70061	40013	30013	10000	30010	10000	1859733	694745	40010	30020	10000	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40025	70079	40021	30019	10002	30045	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60114	20034	30009	10000	30010

Test 4: throughput

Count: 8

Code:

  ldrsh w0, [x6, w7, sxtw]
  ldrsh w0, [x6, w7, sxtw]
  ldrsh w0, [x6, w7, sxtw]
  ldrsh w0, [x6, w7, sxtw]
  ldrsh w0, [x6, w7, sxtw]
  ldrsh w0, [x6, w7, sxtw]
  ldrsh w0, [x6, w7, sxtw]
  ldrsh w0, [x6, w7, sxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40178	80129	101	80028	100	80008	300	256580	80108	200	80012	200	160024	1	80000	100
80204	40547	80221	101	80120	100	80008	300	641114	80108	200	80012	200	160024	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	160024	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	160024	1	80000	100
80204	40054	80101	101	80000	100	80008	300	640610	80108	200	80012	200	160252	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	160024	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	160024	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	160024	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	160024	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	160024	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40285	80043	11	80032	10	80008	30	400262	80018	20	80012	20	160000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	160000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	160000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	160000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	160000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	160000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	160000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	160024	1	80000	10
80024	40055	80011	11	80000	10	80000	30	640166	80010	20	80000	20	160000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	80010	20	80000	20	160000	1	80000	10

LDRSH (register, sxtw, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations