Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ORR (immediate, 64-bit)

Test 1: uops

Code:

  orr x0, x0, #3
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
100410301001100110002560310001000100010011000
100410301001100110002560310001000100010011000
100410301001100110002560310001000100010011000
100410301001100110002560310001000104810151000
100410301001100110002560310001000100010011000
100410301001100110002560310001000100010011000
100410301001100110002560310001000100010011000
100410301001100110002560310001000100010011000
100410301001100110002560310001000100010011000
100410301001100110002560310001000100010011000

Test 2: Latency 1->2

Code:

  orr x0, x0, #3
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204100301010110101101082593291010710214102131000110100
10204100301010110101101072595391010710212102121000110100
10204100301010110101101072595391010710212102121000110100
10204100301010110101101072595391010710212102121000110100
10204100301010110101101072595391010710212102121000110100
10204100301010110101101072595391010710212102121000110100
10204100301010110101101072598481015010262102121000110100
10204100301010110101101072595391010710212102121000110100
10204100301010110101101072595391010710212102121000110100
10204100301010110101101072595391010710212102121000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024100301002110021100282594741002010020100201001110010
10024101301006510065101102595911002010020100201001110010
10024100301002110021100202595911002010020100201001110010
10024100301002110021100202595911002010020100201001110010
10024100301002110021100202595911002010020100201001110010
10024100301002110021100202595911002010020100201001110010
10024100301002110021100202595911002010020100201001110010
10024100301002110021100202595911002010020100201001110010
10024100301002110021100202595911002010020100201001110010
10024100301002110021100202595911002010020100661003210010

Test 3: throughput

Count: 8

Code:

  orr x0, x8, #3
  orr x1, x8, #3
  orr x2, x8, #3
  orr x3, x8, #3
  orr x4, x8, #3
  orr x5, x8, #3
  orr x6, x8, #3
  orr x7, x8, #3
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
80204268938011580115801202403608012080224802228001580100
80204267428011580115801202403608012080224802248001580100
80204267378011580115801202403608012080224802248001580100
80204267378011580115801202403608012080224802768005780100
80204267378011580115801202403608012080224802248001580100
80204267378011580115801202403608012080224802228001480100
80204267378011580115801202403608012080224802248001580100
80204267378011580115801202403608012080224802248001580100
80204267378011580115801202403608012080224802248001580100
80204267378011580115801202403608012080224802248001580100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
80024278868003880038800432614858004480048800208001180010
80024267698002180021800202774048002080020800208001180010
80024267178002180021800202774048002080020800208001180010
80024267178002180021800202774048002080020800208001180010
80024267178002180021800202774048002080020800208001180010
80024267178002180021800202774048002080020800208001180010
80024267178002180021800202774048002080020800208001180010
80024267178002180021800202774048002080020800208001180010
80024267178002180021800202774048002080020800208001180010
80024267178002180021800202774048002080020800208001180010