Icestorm: NEGS (register, lsr, 64-bit) measurements

Code:

  negs x0, x0, lsr #17

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
1004	2030	2001	2001	1000	0	52265	0	0	1000	1000	0	0	1000	0	0	2001	0	0	1000
1004	2030	2001	2001	1000	0	52265	0	0	1000	1000	0	0	1000	0	0	2001	0	0	1000
1004	2030	2001	2001	1000	0	52265	0	0	1000	1000	0	0	1000	0	0	2001	0	0	1000
1004	2030	2001	2001	1000	0	52265	0	0	1000	1000	0	0	1000	0	0	2001	0	0	1000
1004	2030	2001	2001	1000	0	52265	0	0	1000	1000	0	0	1000	0	0	2001	0	0	1000
1004	2030	2001	2001	1000	0	52265	0	0	1000	1000	0	0	1000	0	0	2001	0	0	1000
1004	2030	2001	2001	1000	0	52265	0	0	1000	1000	0	0	1000	0	0	2001	0	0	1000
1004	2030	2001	2001	1000	0	52265	0	0	1000	1000	0	0	1000	0	0	2001	0	0	1000
1004	2030	2001	2001	1000	0	52265	0	0	1000	1000	0	0	1000	0	0	2001	0	0	1000
1004	2030	2001	2001	1000	0	52265	0	0	1000	1000	0	0	1000	0	0	2001	0	0	1000

Test 2: Latency 1->2

Code:

  negs x0, x0, lsr #17

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	20030	20101	20101	10104	529001	10104	10206	10206	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	10208	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	10208	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	10208	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	10208	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	10244	20016	10100
10204	20030	20101	20101	10104	529087	10104	10208	10208	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	10208	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	10208	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	10208	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10024	20030	20021	20021	10025	529215	10025	10030	10020	0	20011	0	0	10010
10024	20030	20021	20021	10020	529249	10020	10020	10020	0	20011	0	0	10010
10024	20030	20021	20021	10020	529249	10020	10020	10020	0	20011	0	0	10010
10024	20030	20021	20021	10020	529249	10020	10020	10020	0	20011	0	0	10010
10024	20030	20021	20021	10020	529249	10020	10020	10020	0	20011	0	0	10010
10024	20030	20021	20021	10020	529249	10020	10020	10020	0	20011	0	0	10010
10024	20030	20021	20021	10020	529249	10020	10020	10172	0	20095	0	0	10010
10024	20030	20021	20021	10020	529249	10020	10020	10020	0	20011	0	0	10010
10024	20030	20021	20021	10020	529249	10020	10020	10020	0	20011	0	0	10010
10024	20030	20021	20021	10020	529249	10020	10020	10020	0	20011	0	0	10010

Test 3: Latency 3->2

Chain cycles: 1

Code:

  negs x0, x1, lsr #17
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	30030	30101	30101	20106	789233	20105	20212	20214	30001	20100
20204	30030	30101	30101	20105	789310	20105	20210	20212	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	20257	30016	20100
20204	30030	30101	30101	20105	789369	20105	20212	20212	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	20212	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	20212	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	20212	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	20212	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	20212	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	20212	30001	20100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	30030	30011	30011	20015	789401	20015	20032	20020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	20020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	20020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	20020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	20020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	20020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	20020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	20020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	20020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	20020	30001	20010

Test 4: throughput

Count: 8

Code:

  negs x0, x8, lsr #17
  negs x1, x8, lsr #17
  negs x2, x8, lsr #17
  negs x3, x8, lsr #17
  negs x4, x8, lsr #17
  negs x5, x8, lsr #17
  negs x6, x8, lsr #17
  negs x7, x8, lsr #17

Initialization

  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	53416	160116	160116	0	0	80122	0	1099575	80123	80224	80224	160014	80100
80204	53404	160114	160114	0	0	80123	0	1100076	80123	80224	80224	160014	80100
80204	53404	160114	160114	0	0	80123	0	1100076	80123	80224	80224	160014	80100
80204	53404	160114	160114	0	0	80123	0	1100076	80123	80224	80224	160014	80100
80204	53404	160114	160114	0	0	80123	0	1100076	80123	80224	80224	160014	80100
80204	53404	160114	160114	0	0	80123	0	1100076	80123	80224	80224	160014	80100
80204	53404	160114	160114	0	0	80123	0	1100076	80123	80224	80224	160014	80100
80204	53404	160114	160114	0	0	80123	0	1100297	80165	80266	80224	160014	80100
80204	53404	160114	160114	0	0	80123	0	1100076	80123	80224	80264	160062	80100
80204	53404	160114	160114	0	0	80123	0	1100076	80123	80224	80224	160018	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6671

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	53395	160045	160045	80050	1104887	80050	80050	80020	160011	80010
80024	53371	160021	160021	80020	1107732	80020	80020	80020	160011	80010
80024	53371	160021	160021	80020	1107732	80020	80020	80020	160011	80010
80024	53371	160021	160021	80020	1107732	80020	80020	80020	160011	80010
80024	53371	160021	160021	80020	1107732	80020	80020	80020	160011	80010
80024	53371	160021	160021	80020	1107732	80020	80020	80020	160011	80010
80024	53371	160021	160021	80020	1107732	80020	80020	80020	160011	80010
80024	53371	160021	160021	80020	1107732	80020	80020	80020	160011	80010
80024	53371	160021	160021	80020	1107732	80020	80020	80020	160011	80010
80024	53371	160021	160021	80020	1107732	80020	80020	80020	160011	80010

NEGS (register, lsr, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 3->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations