Icestorm: AXFLAG measurements

Code:

  axflag

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)
1004	1030	1001	1001	1000	25192	1000	1000	1000	1001
1004	1030	1001	1001	1000	25192	1000	1000	1000	1001
1004	1030	1001	1001	1000	25192	1000	1000	1000	1001
1004	1030	1001	1001	1000	25192	1000	1000	1000	1001
1004	1030	1001	1001	1000	25192	1000	1000	1000	1001
1004	1030	1001	1001	1000	25192	1000	1000	1000	1001
1004	1030	1001	1001	1000	25192	1000	1000	1000	1001
1004	1030	1001	1001	1000	25192	1000	1000	1000	1001
1004	1030	1001	1001	1000	25192	1000	1000	1000	1001
1004	1030	1001	1001	1000	25192	1000	1000	1000	1001

Test 2: Latency 1->1

Code:

  axflag

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10201	10201	10207	254581	10211	10214	10214	10101	100
10204	10030	10201	10201	10208	254549	10211	10214	10208	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	10208	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	10208	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	10208	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	10208	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	10208	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	10208	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	10208	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	10208	10101	100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10029	255052	10029	10030	10030	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	10020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	10020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	10020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	10020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	10020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	10020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	10020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	10020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	10020	10011	10

Test 3: throughput

Count: 8

Code:

  ands xzr, xzr, xzr
  axflag
  ands xzr, xzr, xzr
  axflag
  ands xzr, xzr, xzr
  axflag
  ands xzr, xzr, xzr
  axflag
  ands xzr, xzr, xzr
  axflag
  ands xzr, xzr, xzr
  axflag
  ands xzr, xzr, xzr
  axflag
  ands xzr, xzr, xzr
  axflag

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.7888

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
160204	63340	160110	160110	160116	689422	160121	160222	80209	160013	100
160204	62598	160117	160117	160122	682955	160270	160372	80210	160015	100
160204	63081	160114	160114	160120	690787	160118	160220	80209	160012	100
160205	63160	160151	160151	160159	689536	160118	160220	80210	160016	100
160204	63125	160118	160118	160123	688776	160197	160297	80210	160016	100
160204	63133	160115	160115	160120	689081	160116	160216	80210	160012	100
160204	63133	160115	160115	160120	688303	160118	160218	80209	160013	100
160204	63154	160113	160113	160117	689081	160116	160216	80209	160012	100
160204	63091	160112	160112	160118	687220	160120	160220	80210	160011	100
160204	62969	160268	160268	160273	687569	160120	160224	80210	160012	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.7829

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
160024	64564	160023	160023	0	0	160030	0	701336	160030	160042	80020	160001	10
160024	63221	160011	160011	0	0	160010	0	671956	160010	160020	80020	160001	10
174462	93935	175202	170105	55	5042	169937	46	681803	160065	160077	80032	160016	10
160024	62872	160011	160011	0	0	160010	0	671671	160010	160020	80020	160001	10
160025	62715	160063	160063	0	0	160066	0	670844	160010	160020	80020	160001	10
160024	62685	160011	160011	0	0	160010	0	671670	160010	160020	80020	160001	10
160024	62655	160011	160011	0	0	160010	0	670638	160010	160020	80020	160001	10
160024	62687	160011	160011	0	0	160010	0	671191	160010	160020	80020	160001	10
160024	62665	160011	160011	0	0	160010	0	669974	160010	160020	80020	160001	10
160024	63075	160011	160011	0	0	160010	0	670092	160049	160059	80020	160001	10

Test 4: throughput

Count: 4

Code:

  fcmp s0, s0
  axflag
  axflag
  axflag
  axflag

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5998

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
50204	24001	50104	40101	10003	40109	10003	315712	40017	50118	40214	10004	40212	20008	40002	100
50205	24046	50145	40134	10011	40148	10013	315095	40012	50112	40209	10003	40212	20008	40002	100
50204	23999	50106	40103	10003	40109	10003	315001	40017	50116	40212	10004	40209	20006	40001	100
50204	24003	50105	40102	10003	40109	10003	315063	40013	50112	40209	10003	40212	20008	40003	100
50204	23993	50103	40101	10002	40109	10003	315619	40017	50116	40212	10004	40212	20008	40001	100
50204	24000	50104	40101	10003	40109	10003	315306	40017	50116	40212	10004	40212	20008	40002	100
50204	23986	50105	40102	10003	40109	10003	314862	40012	50112	40209	10003	40216	20008	40005	100
50204	23999	50105	40102	10003	40112	10004	314773	40012	50112	40209	10003	40216	20008	40005	100
50204	23992	50104	40101	10003	40109	10003	315271	40017	50116	40212	10004	40212	20008	40001	100
50204	24007	50104	40101	10003	40109	10003	315434	40012	50112	40209	10003	40212	20008	40002	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5998

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
50024	24098	50018	40015	10003	40020	10003	316129	40022	50032	40037	10005	40020	20000	40001	10
50024	24019	50011	40011	10000	40010	10000	316523	40000	50010	40020	10000	40020	20000	40001	10
50024	24003	50011	40011	10000	40010	10000	316456	40000	50010	40020	10000	40020	20000	40001	10
50024	23990	50011	40011	10000	40010	10000	315557	40000	50010	40020	10000	40020	20000	40001	10
50024	23953	50011	40011	10000	40010	10000	316269	40000	50010	40020	10000	40020	20000	40001	10
50024	24027	50011	40011	10000	40010	10000	316247	40000	50010	40020	10000	40020	20000	40001	10
50024	23999	50011	40011	10000	40010	10000	316677	40000	50010	40020	10000	40020	20000	40001	10
50024	23957	50011	40011	10000	40010	10000	315751	40000	50010	40020	10000	40020	20000	40001	10
50024	23959	50011	40011	10000	40010	10000	316129	40000	50010	40020	10000	40020	20000	40001	10
50024	23973	50011	40011	10000	40010	10000	316685	40000	50010	40020	10000	40020	20000	40001	10

Test 5: throughput

Count: 7

Code:

  ands xzr, xzr, xzr
  axflag
  axflag
  axflag
  axflag
  axflag
  axflag
  axflag

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5567

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	39057	80104	80104	80108	550299	80120	80222	70213	80007	100
80205	38944	80134	80134	80148	550005	80117	80218	70213	80008	100
80205	38981	80139	80139	80152	548826	80108	80208	70214	80008	100
80204	38964	80106	80106	80116	550503	80116	80216	70210	80005	100
80204	38989	80108	80108	80119	550000	80116	80216	70214	80004	100
80204	38973	80103	80103	80111	551999	80116	80216	70214	80004	100
80204	38980	80103	80103	80111	550183	80116	80216	70214	80004	100
80204	39009	80108	80108	80116	550420	80116	80216	70210	80003	100
80204	38918	80106	80106	80116	548462	80114	80216	70214	80004	100
80204	38970	80104	80104	80114	549968	80111	80212	70214	80007	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5557

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	39134	80027	80027	80036	548110	80020	80020	70020	80011	10
80024	38885	80021	80021	80020	547544	80020	80020	70020	80011	10
80024	38878	80021	80021	80020	546632	80020	80020	70020	80011	10
80024	38886	80021	80021	80020	544094	80020	80020	70020	80011	10
80024	38886	80021	80021	80020	546432	80020	80020	70087	80088	10
80024	38871	80021	80021	80020	546691	80020	80020	70020	80011	10
80024	38885	80021	80021	80020	546822	80020	80020	70055	80051	10
80024	38871	80021	80021	80020	546938	80020	80020	70020	80011	10
80024	38901	80021	80021	80020	546228	80020	80020	70020	80011	10
80024	38920	80021	80021	80020	546691	80020	80020	70020	80011	10

AXFLAG

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations