Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ADD (uxtb, 32-bit)

Test 1: uops

Code:

  add w0, w0, w1, uxtb
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005260310331042200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000

Test 2: Latency 1->2

Code:

  add w0, w0, w1, uxtb
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204200302010120101101045291001010410210203142001610100
10204200302010120101101045291861010410212202242000110100
10204200302010120101101045291861010410212202242000110100
10204200302010120101101045291861010410212202242000110100
10204200302010120101101045291861010410212202242000110100
10204200302010120101101045291861010410212202242000110100
10204200302010120101101045291861010410212202242000110100
10204200302010120101101045291861010410212202242000110100
10204200302010120101101045291861010410212202242000110100
10204200302010120101101045291861010410212202242000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024200302002120021100255292211002510034200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010

Test 3: Latency 1->3

Code:

  add w0, w1, w0, uxtb
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
1020420030201012010110104052910000101041021000202240200010010100
1020420030201012010110104052918600101041021200202240200010010100
1020420030201012010110104052918600101041021200202240200010010100
1020420030201012010110104052918600101041021200202240200010010100
1020420030201012010110104052918600101041021200202240200010010100
1020420030201012010110104052918600101041021200202240200010010100
1020420030201012010110104052918600101041021200202240200010010100
1020420030201012010110104052918600101041021200202240200010010100
1020420030201012010110104052918600101041021200202240200010010100
1020420030201012010110104052918600101041021200202240200010010100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024200302002120021100255292201002510034200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010

Test 4: throughput

Count: 8

Code:

  add w0, w8, w9, uxtb
  add w1, w8, w9, uxtb
  add w2, w8, w9, uxtb
  add w3, w8, w9, uxtb
  add w4, w8, w9, uxtb
  add w5, w8, w9, uxtb
  add w6, w8, w9, uxtb
  add w7, w8, w9, uxtb
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
8020453404160117160117801301360297801298023416027216001780100
8020453404160117160117801301360838801308023616027216001780100
8020453404160117160117801301360838801308023616027216001780100
8020453404160117160117801301360838801308023616027216001780100
8020453404160117160117801301360838801308023616027216001780100
8020453404160117160117801301360838801308023616027216001780100
8020453404160117160117801301360838801308023616027216001780100
8020453404160117160117801301361165801778028816027216001780100
8020453404160117160117801301360838801308023616027216001780100
8020453404160117160117801301360838801308023616027216001780100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6671

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
8002453378160038160038800501359646800208002016002016001180010
8002453371160021160021800201359903800208002016002016001180010
8002453371160021160021800201359903800208002016002016001180010
8002453371160021160021800201359903800208002016002016001180010
8002453371160021160021800201359903800208002016002016001180010
8002653433160087160087801001359646800208002016002016001180010
8002453371160021160021800201359903800208002016002016001180010
8002453371160021160021800201359903800208002016002016001180010
8002453371160021160021800201359903800208002016002016001180010
8002453371160021160021800201359903800208002016002016001180010