Icestorm: LDRH (register, lsl) measurements

Code:

  ldrh w0, [x6, x7, lsl #1]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	683	1029	1	1028	1000	8238	1000	1000	2000	1	1000
1004	554	1001	1	1000	1000	8112	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	7715	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	8076	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	8166	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	2000	1	1000
1004	554	1001	1	1000	1000	8112	1000	1000	2000	1	1000
1004	576	1001	1	1000	1000	8166	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	2000	1	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrh w0, [x6, x7, lsl #1]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70150	40108	30107	10001	30130	10003	1859539	693896	40106	30210	10004	60220	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10015	1860140	725161	40150	30248	10017	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70165	40018	30017	10001	30040	10003	1859623	693696	40016	30030	10004	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10015	1859987	705634	40060	30068	10017	60020	20000	30003	10000	30010
40025	70077	40021	30019	10002	30045	10000	1860873	730138	40010	30020	10000	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10015	1860016	694855	40060	30071	10017	60020	20000	30003	10000	30010

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrh w0, [x6, x7, lsl #1]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70153	40108	30107	10001	30130	10003	1859533	693921	40106	30210	10004	60220	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40205	70077	40111	30109	10002	30135	10003	1860175	694305	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859689	694103	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0043

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70162	40018	30017	10001	30040	10003	1859677	693718	0	40016	30030	10004	0	60350	20114	30039	10000	30010
40024	70071	40013	30013	10000	30013	10003	1859671	694738	0	40016	30032	10004	0	60020	20000	30003	10000	30010
40024	70074	40014	30014	10000	30013	10000	1859658	693674	0	40010	30020	10000	0	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	0	40010	30020	10000	0	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	0	40010	30020	10000	0	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	0	40010	30020	10000	0	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10015	1860070	694875	0	40060	30071	10017	0	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	0	40010	30020	10000	0	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	0	40010	30020	10000	0	60020	20000	30003	10000	30010
40024	70053	40013	30013	10000	30010	10052	1866775	697495	0	40194	30176	10052	0	60020	20000	30003	10000	30010

Test 4: throughput

Count: 8

Code:

  ldrh w0, [x6, x7, lsl #1]
  ldrh w0, [x6, x7, lsl #1]
  ldrh w0, [x6, x7, lsl #1]
  ldrh w0, [x6, x7, lsl #1]
  ldrh w0, [x6, x7, lsl #1]
  ldrh w0, [x6, x7, lsl #1]
  ldrh w0, [x6, x7, lsl #1]
  ldrh w0, [x6, x7, lsl #1]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40191	80133	101	80032	100	80008	300	328262	80108	200	80012	200	160028	1	80000	100
80204	40057	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40247	80033	11	80022	10	80008	30	400190	0	80018	20	80012	0	20	160000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	0	80010	20	80000	0	20	160000	1	80000	10
80024	40136	80011	11	80000	10	80000	30	640472	0	80010	20	80000	0	20	160000	1	80000	10
80024	40063	80011	11	80000	10	80000	30	640166	0	80010	20	80000	0	20	160000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	0	80010	20	80000	0	20	160000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	0	80010	20	80000	0	20	160000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	0	80010	20	80000	0	20	160000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	0	80010	20	80000	0	20	160000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	0	80010	20	80000	0	20	160000	1	80000	10
80024	40050	80011	11	80000	10	80058	30	410426	0	80068	20	80071	0	20	160000	1	80000	10

LDRH (register, lsl)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations