Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

PRFM (register, PSTL3KEEP)

Test 1: uops

Code:

  prfm pstl3keep, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1004	2115	1001	1	1000	1000	34906	1000	1000	1000	1	1000
1004	2097	1001	1	1000	1000	34906	1000	1000	1000	1	1000
1004	2097	1001	1	1000	1000	34906	1000	1000	1000	1	1000
1004	2097	1001	1	1000	1000	34906	1000	1000	1000	1	1000
1004	2097	1001	1	1000	1000	34906	1000	1000	1000	1	1000
1004	2097	1001	1	1000	1000	34906	1000	1000	1000	1	1000
1004	2097	1001	1	1000	1000	34906	1000	1000	1000	1	1000
1004	2097	1001	1	1000	1000	34906	1000	1000	1000	1	1000
1004	2097	1001	1	1000	1000	34906	1000	1000	1000	1	1000
1004	2097	1001	1	1000	1000	34906	1000	1000	1000	1	1000

Test 2: throughput

Code:

  prfm pstl3keep, [x6]
  add x6, x6, 64

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0143

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20204	20783	20103	10103	10000	10108	10000	61139	351287	20101	10203	10003	10204	10004	10001	10000	10100
20204	20135	20101	10101	10000	10102	10000	61156	351501	20102	10204	10004	10204	10004	10001	10000	10100
20204	20089	20101	10101	10000	10102	10000	61200	351151	20106	10208	10008	10208	10008	10002	10000	10100
20204	20086	20101	10101	10000	10102	10000	61096	351105	20102	10204	10004	10204	10004	10001	10000	10100
20204	20088	20101	10101	10000	10102	10000	61082	351429	20102	10204	10004	10204	10004	10001	10000	10100
20204	20091	20101	10101	10000	10102	10000	61156	351375	20102	10204	10004	10210	10010	10003	10000	10100
20204	20079	20101	10101	10000	10102	10000	61246	350853	20102	10204	10004	10204	10004	10001	10000	10100
20204	20139	20101	10101	10000	10102	10004	61223	350429	20114	10212	10012	10208	10008	10002	10000	10100
20204	20206	20102	10102	10000	10103	10000	61284	350727	20103	10205	10005	10208	10008	10002	10000	10100
20204	20120	20102	10102	10000	10104	10000	61296	351067	20104	10206	10006	10204	10004	10001	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0201

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20024	20851	20012	10012	10000	10016	10000	60916	352057	20015	10027	10007	10020	10000	10001	10000	10010
20024	20201	20011	10011	10000	10010	10000	60875	352093	20010	10020	10000	10020	10000	10001	10000	10010
20024	20201	20011	10011	10000	10010	10000	60875	352093	20010	10020	10000	10020	10000	10001	10000	10010
20024	20201	20011	10011	10000	10010	10000	60875	352093	20010	10020	10000	10020	10000	10001	10000	10010
20024	20201	20011	10011	10000	10010	10000	60875	352093	20010	10020	10000	10020	10000	10001	10000	10010
20024	20201	20011	10011	10000	10010	10000	60875	352093	20010	10020	10000	10020	10000	10001	10000	10010
20024	20201	20011	10011	10000	10010	10000	60875	352093	20010	10020	10000	10020	10000	10001	10000	10010
20024	20201	20011	10011	10000	10010	10000	60875	352093	20010	10020	10000	10020	10000	10001	10000	10010
20024	20201	20011	10011	10000	10010	10000	60875	352093	20010	10020	10000	10020	10000	10001	10000	10010
20024	20201	20011	10011	10000	10010	10000	60875	352093	20010	10020	10000	10020	10000	10001	10000	10010

Test 3: throughput

Code:

  prfm pstl3keep, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0503

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10204	20504	10101	101	10000	100	10049	300	354611	10149	200	10065	200	10012	1	10000	100
10204	20503	10101	101	10000	100	10006	300	357346	10106	200	10012	200	10012	1	10000	100
10204	20503	10101	101	10000	100	10006	300	357346	10106	200	10012	200	10012	1	10000	100
10204	20503	10101	101	10000	100	10006	300	357346	10106	200	10012	200	10012	1	10000	100
10204	20507	10101	101	10000	100	10006	300	357346	10106	200	10012	200	10012	1	10000	100
10204	20503	10101	101	10000	100	10006	300	357346	10106	200	10012	200	10012	1	10000	100
10204	20503	10101	101	10000	100	10006	300	357346	10106	200	10012	200	10012	1	10000	100
10204	20503	10101	101	10000	100	10006	300	357346	10106	200	10012	200	10012	1	10000	100
10204	20503	10101	101	10000	100	10006	300	357346	10106	200	10012	200	10012	1	10000	100
10204	20503	10101	101	10000	100	10006	300	357346	10106	200	10012	200	10012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0503

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10024	19506	10011	11	10000	10	10004	30	334496	10014	20	10012	20	10000	1	10000	10
10024	19282	10011	11	10000	10	10000	30	337250	10010	20	10000	20	10000	1	10000	10
10024	19266	10011	11	10000	10	10000	30	335426	10010	20	10000	20	10000	1	10000	10
10024	19387	10011	11	10000	10	10000	30	337810	10010	20	10000	20	10000	1	10000	10
10024	20472	10011	11	10000	10	10000	30	356832	10010	20	10004	20	10000	1	10000	10
10024	20462	10011	11	10000	10	10000	30	357084	10010	20	10000	20	10000	1	10000	10
10024	20503	10011	11	10000	10	10000	30	357322	10010	20	10000	20	10000	1	10000	10
10024	20503	10011	11	10000	10	10000	30	357322	10010	20	10000	20	10000	1	10000	10
10024	20503	10011	11	10000	10	10000	30	357322	10010	20	10000	20	10000	1	10000	10
10024	20503	10011	11	10000	10	10000	30	357322	10010	20	10000	20	10000	1	10000	10