Icestorm: ORR (register, asr, 32-bit) measurements

Code:

  orr w0, w0, w1, asr #17

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000

Test 2: Latency 1->2

Code:

  orr w0, w0, w1, asr #17

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	20030	20101	20101	10104	529100	10104	10210	20224	20001	10100
10204	20030	20101	20101	10104	529186	10104	10212	20224	20001	10100
10204	20030	20101	20101	10104	529186	10104	10212	20224	20001	10100
10205	20060	20115	20115	10137	529126	10104	10210	20224	20001	10100
10204	20030	20101	20101	10104	529186	10104	10212	20224	20001	10100
10204	20030	20101	20101	10104	529186	10104	10212	20224	20001	10100
10204	20030	20101	20101	10104	529186	10104	10212	20224	20001	10100
10204	20030	20101	20101	10104	529186	10104	10212	20224	20001	10100
10204	20030	20101	20101	10104	529186	10104	10212	20224	20001	10100
10204	20030	20101	20101	10104	529186	10104	10212	20224	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	20030	20021	20021	10025	529197	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10025	20060	20035	20035	10058	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010

Test 3: Latency 1->3

Code:

  orr w0, w1, w0, asr #17

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	20030	20101	20101	10104	0	529100	0	10104	10210	0	20224	20001	10100
10204	20030	20101	20101	10104	0	529186	0	10104	10212	0	20224	20001	10100
10204	20030	20101	20101	10104	0	529186	0	10104	10212	0	20224	20001	10100
10204	20030	20101	20101	10104	0	529186	0	10104	10212	0	20224	20001	10100
10204	20030	20101	20101	10104	0	529186	0	10104	10212	0	20224	20001	10100
10204	20030	20101	20101	10104	0	529186	0	10104	10212	0	20224	20001	10100
10204	20030	20101	20101	10104	0	529186	0	10104	10212	0	20224	20001	10100
10204	20030	20101	20101	10104	0	529186	0	10104	10212	0	20224	20001	10100
10204	20030	20101	20101	10104	0	529186	0	10104	10212	0	20224	20001	10100
10204	20030	20101	20101	10104	0	529186	0	10104	10212	0	20224	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	20030	20021	20021	10025	529220	10025	10034	20044	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20124	20025	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010

Test 4: throughput

Count: 8

Code:

  orr w0, w8, w9, asr #17
  orr w1, w8, w9, asr #17
  orr w2, w8, w9, asr #17
  orr w3, w8, w9, asr #17
  orr w4, w8, w9, asr #17
  orr w5, w8, w9, asr #17
  orr w6, w8, w9, asr #17
  orr w7, w8, w9, asr #17

Initialization

  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
82358	71858	161845	161208	637	81122	1360290	80129	80234	160272	160017	80100
80204	53415	160116	160116	0	80129	1360838	80130	80236	160272	160017	80100
80205	53447	160161	160161	0	80177	1360838	80130	80236	160272	160017	80100
80204	53404	160117	160117	0	80130	1360838	80130	80236	160272	160017	80100
80204	53404	160117	160117	0	80130	1360838	80130	80236	160272	160017	80100
80204	53404	160117	160117	0	80130	1360838	80130	80236	160272	160017	80100
80204	53404	160117	160117	0	80130	1360838	80130	80236	160272	160017	80100
80204	53404	160117	160117	0	80130	1360838	80130	80236	160272	160017	80100
80204	53404	160117	160117	0	80130	1360838	80130	80236	160384	160065	80100
80204	53404	160117	160117	0	80130	1360838	80130	80236	160376	160059	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6671

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	53402	160039	160039	80051	0	1359975	0	80051	80058	0	160020	160011	80010
80024	53371	160021	160021	80020	0	1359903	0	80020	80020	0	160020	160011	80010
80025	53408	160082	160082	80097	0	1359903	0	80020	80020	0	160020	160011	80010
80024	53371	160021	160021	80020	0	1360530	0	80096	80108	0	160020	160011	80010
80024	53371	160021	160021	80020	0	1359903	0	80020	80020	0	160020	160011	80010
80024	53371	160021	160021	80020	0	1359903	0	80020	80020	0	160020	160011	80010
80024	53371	160021	160021	80020	0	1359903	0	80020	80020	0	160020	160011	80010
80024	53371	160021	160021	80020	0	1359903	0	80020	80020	0	160020	160011	80010
80024	53371	160021	160021	80020	0	1359903	0	80020	80020	0	160020	160011	80010
80024	53371	160021	160021	80020	0	1359903	0	80020	80020	0	160020	160011	80010

ORR (register, asr, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations