Icestorm: CFINV measurements

Code:

  cfinv

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)
1004	1030	1001	1001	1000	25192	1000	1000	1000	1001
1004	1030	1001	1001	1000	25192	1000	1000	1000	1001
1004	1030	1001	1001	1000	25192	1000	1000	1000	1001
1004	1030	1001	1001	1000	25192	1000	1000	1000	1001
1004	1030	1001	1001	1000	25192	1000	1000	1000	1001
1004	1030	1001	1001	1000	25192	1000	1000	1000	1001
1004	1030	1001	1001	1000	25192	1000	1000	1000	1001
1004	1030	1001	1001	1000	25192	1000	1000	1000	1001
1004	1030	1001	1001	1000	25192	1000	1000	1000	1001
1004	1030	1001	1001	1000	25192	1000	1000	1000	1001

Test 2: Latency 1->1

Code:

  cfinv

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10201	10201	10208	254411	10214	10214	10214	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	10208	10101	100
10204	10078	10222	10222	10247	254709	10208	10208	10208	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	10208	10101	100
10204	10030	10201	10201	10208	255191	10247	10247	10247	10122	100
10204	10030	10201	10201	10208	254709	10208	10208	10208	10101	100
10204	10030	10201	10201	10208	254568	10211	10214	10214	10101	100
10204	10030	10201	10201	10211	254709	10208	10208	10208	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	10208	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	10208	10101	100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10029	255052	10029	10030	10032	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	10020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	10020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	10020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	10020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	10020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	10020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	10020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	10020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	10020	10011	10

Test 3: throughput

Count: 8

Code:

  ands xzr, xzr, xzr
  cfinv
  ands xzr, xzr, xzr
  cfinv
  ands xzr, xzr, xzr
  cfinv
  ands xzr, xzr, xzr
  cfinv
  ands xzr, xzr, xzr
  cfinv
  ands xzr, xzr, xzr
  cfinv
  ands xzr, xzr, xzr
  cfinv
  ands xzr, xzr, xzr
  cfinv

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.7890

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
160204	63293	160112	160112	160118	685486	160117	160218	80209	160015	100
160204	63143	160113	160113	160118	689654	160121	160222	80210	160015	100
160205	63183	160153	160153	160159	670982	160119	160221	80209	160014	100
160204	63134	160115	160115	160120	689652	160118	160220	80210	160012	100
160204	63144	160115	160115	160120	688893	160120	160220	80210	160013	100
160204	63134	160115	160115	160120	686737	160124	160224	80210	160012	100
160204	63122	160112	160112	160118	687919	160118	160220	80209	160017	100
160204	63119	160111	160111	160115	672046	160125	160227	80210	160012	100
160204	63096	160112	160112	160118	687376	160118	160220	80209	160012	100
160204	63111	160112	160112	160118	687485	160118	160220	80210	160012	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.7825

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
160024	64413	160026	160026	160033	685679	160010	160020	80020	160001	10
160024	63098	160011	160011	160010	671432	160010	160020	80020	160001	10
160024	62545	160011	160011	160010	671957	160010	160020	80020	160001	10
160024	62561	160011	160011	160010	671698	160010	160020	80020	160001	10
160024	62573	160011	160011	160010	671001	160010	160020	80020	160001	10
160025	62586	160064	160064	160068	671250	160010	160020	80020	160001	10
160024	62659	160011	160011	160010	670929	160010	160020	80020	160001	10
160024	62626	160011	160011	160010	669616	160010	160020	80020	160001	10
160024	62657	160011	160011	160010	670730	160010	160020	80020	160001	10
160024	62653	160011	160011	160010	670672	160010	160020	80020	160001	10

Test 4: throughput

Count: 4

Code:

  fcmp s0, s0
  cfinv
  cfinv
  cfinv
  cfinv

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5998

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
50204	24019	50109	40106	10003	40117	10005	315580	40022	50122	40217	10005	40211	20006	40003	100
50204	23994	50106	40103	10003	40114	10004	315896	40017	50116	40212	10004	40212	20008	40002	100
50204	24013	50104	40101	10003	40112	10004	315269	40018	50116	40212	10004	40209	20006	40001	100
50204	23979	50106	40103	10003	40109	10003	315289	40012	50112	40209	10003	40212	20008	40001	100
50204	23993	50103	40101	10002	40109	10003	315563	40012	50112	40209	10003	40209	20006	40003	100
50204	23987	50104	40101	10003	40112	10004	315465	40017	50116	40212	10004	40212	20008	40002	100
50204	23994	50103	40101	10002	40112	10004	314862	40012	50112	40209	10003	40212	20008	40001	100
50204	23984	50103	40101	10002	40109	10003	315068	40017	50116	40212	10004	40209	20006	40001	100
50204	23993	50103	40101	10002	40109	10003	315563	40012	50112	40209	10003	40212	20008	40002	100
50204	23992	50105	40102	10003	40112	10004	315283	40012	50112	40209	10003	40209	20006	40003	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5998

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
50024	24195	50013	40011	10002	40019	10003	316349	40000	50010	40020	10000	40020	20000	40001	10
50024	23973	50011	40011	10000	40010	10000	316443	40000	50010	40020	10000	40020	20000	40001	10
50024	23999	50011	40011	10000	40010	10000	316463	40000	50010	40020	10000	40020	20000	40001	10
50024	23993	50011	40011	10000	40010	10000	315547	40000	50010	40020	10000	40059	20022	40025	10
50024	23954	50011	40011	10000	40010	10000	315067	40000	50010	40020	10000	40020	20000	40001	10
50024	23974	50011	40011	10000	40010	10000	317002	40000	50010	40020	10000	40020	20000	40001	10
50024	23979	50011	40011	10000	40010	10000	316227	40000	50010	40020	10000	40020	20000	40001	10
50024	23971	50011	40011	10000	40010	10000	315455	40000	50010	40020	10000	40020	20000	40001	10
50024	23993	50011	40011	10000	40010	10000	315614	40000	50010	40020	10000	40020	20000	40001	10
50024	23973	50011	40011	10000	40010	10000	316317	40000	50010	40020	10000	40020	20000	40001	10

Test 5: throughput

Count: 7

Code:

  ands xzr, xzr, xzr
  cfinv
  cfinv
  cfinv
  cfinv
  cfinv
  cfinv
  cfinv

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5568

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	39053	80105	80105	80117	550684	80114	80214	70219	80011	100
80204	38926	80106	80106	80115	548468	80108	80208	70207	80003	100
80204	38985	80104	80104	80114	549055	80111	80212	70214	80007	100
80204	39042	80105	80105	80111	547633	80115	80215	70214	80004	100
80204	38944	80106	80106	80116	547996	80114	80216	70214	80008	100
80204	38976	80103	80103	80114	549785	80116	80216	70207	80006	100
80204	38985	80103	80103	80111	546730	80115	80215	70214	80004	100
80204	38918	80106	80106	80116	549838	80114	80216	70210	80003	100
80204	38970	80104	80104	80114	549968	80111	80212	70214	80007	100
80204	38985	80104	80104	80114	549498	80116	80216	70210	80005	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5557

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	39245	80031	80031	80041	0	545567	0	0	80020	80020	0	0	70020	80011	10
80024	38943	80021	80021	80020	0	546907	0	0	80020	80020	0	0	70020	80011	10
80024	38951	80021	80021	80020	0	546904	0	0	80020	80020	0	0	70020	80011	10
80024	38890	80021	80021	80020	0	545187	0	0	80020	80020	0	0	70020	80011	10
80024	38862	80021	80021	80020	0	547567	0	0	80020	80020	0	0	70020	80011	10
80024	38895	80021	80021	80020	0	544663	0	0	80020	80020	0	0	70020	80011	10
80024	38878	80021	80021	80020	0	546559	0	0	80020	80020	0	0	70020	80011	10
80025	38924	80061	80061	80083	0	546603	0	0	80020	80020	0	0	70020	80011	10
80024	38903	80021	80021	80020	0	548151	0	0	80020	80020	0	0	70020	80011	10
80024	38931	80021	80021	80020	0	548138	0	0	80020	80020	0	0	70020	80011	10

CFINV

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations