Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CLREX

Test 1: uops

Code:

  clrex

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	? int output thing (e9)	? ldst retires (ed)
1004	4956	1001	1	1000	1000	86777	1000	1000	1	1000
1004	4956	1001	1	1000	1000	86777	1000	1000	1	1000
1004	4956	1001	1	1000	1000	86777	1000	1000	1	1000
1004	4956	1001	1	1000	1000	86777	1000	1000	1	1000
1004	4956	1001	1	1000	1000	86777	1000	1000	1	1000
1004	4956	1001	1	1000	1000	86777	1000	1000	1	1000
1004	4956	1001	1	1000	1000	86777	1000	1000	1	1000
1004	4956	1001	1	1000	1000	86777	1000	1000	1	1000
1004	4956	1001	1	1000	1000	86777	1000	1000	1	1000
1004	4956	1001	1	1000	1000	86777	1000	1000	1	1000

Test 2: throughput

Code:

  clrex
  add x6, x6, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.9956

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20204	49956	20102	10102	10000	10101	10000	35714	887777	20101	10203	10003	10203	10002	10000	10100
20204	49956	20101	10101	10000	10100	10000	35710	887777	20100	10202	10002	10202	10001	10000	10100
20204	49956	20101	10101	10000	10100	10000	35710	887777	20100	10202	10002	10202	10001	10000	10100
20204	49956	20101	10101	10000	10100	10000	35710	887777	20100	10202	10002	10202	10001	10000	10100
20204	49956	20101	10101	10000	10100	10000	35710	887777	20100	10202	10002	10202	10001	10000	10100
20204	49956	20101	10101	10000	10100	10000	35710	887777	20100	10202	10002	10202	10001	10000	10100
20204	49956	20101	10101	10000	10100	10000	35710	887777	20100	10202	10002	10202	10001	10000	10100
20204	49956	20101	10101	10000	10100	10000	35710	887777	20100	10202	10002	10202	10001	10000	10100
20204	49956	20101	10101	10000	10100	10000	35710	887777	20100	10202	10002	10202	10001	10000	10100
20204	49956	20101	10101	10000	10100	10000	35710	887777	20100	10202	10002	10202	10001	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.9956

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20024	49956	20012	10012	10000	10011	10000	35485	887777	20010	10020	10000	10020	10001	10000	10010
20024	49956	20011	10011	10000	10010	10000	35485	887777	20010	10020	10000	10020	10001	10000	10010
20024	49956	20011	10011	10000	10010	10000	35485	887777	20010	10020	10000	10020	10001	10000	10010
20024	49956	20011	10011	10000	10010	10000	35485	887777	20010	10020	10000	10052	10029	10000	10010
20024	49956	20011	10011	10000	10010	10000	35485	887777	20010	10020	10000	10020	10001	10000	10010
20024	49956	20011	10011	10000	10010	10000	35485	887777	20010	10020	10000	10020	10001	10000	10010
20024	49956	20011	10011	10000	10010	10000	35485	887777	20010	10020	10000	10020	10001	10000	10010
20024	49956	20011	10011	10000	10010	10000	35485	887777	20010	10020	10000	10020	10001	10000	10010
20024	49956	20011	10011	10000	10010	10000	35485	887777	20010	10020	10000	10020	10001	10000	10010
20024	49956	20011	10011	10000	10010	10000	35485	887777	20010	10020	10000	10020	10001	10000	10010

Test 3: throughput

Code:

  clrex

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.9956

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10204	49956	10101	101	10000	100	10000	300	887777	10100	200	10004	200	1	10000	100
10205	49912	10106	103	10003	102	10000	300	887777	10100	200	10004	200	1	10000	100
10204	49956	10101	101	10000	100	10000	300	887777	10100	200	10004	200	1	10000	100
10204	49956	10101	101	10000	100	10000	300	887777	10100	200	10004	200	1	10000	100
10204	49956	10101	101	10000	100	10000	300	887777	10100	200	10004	200	1	10000	100
10204	49956	10101	101	10000	100	10000	300	887777	10100	200	10004	200	1	10000	100
10204	49956	10101	101	10000	100	10000	300	887777	10100	200	10004	200	1	10000	100
10204	49956	10101	101	10000	100	10000	300	887777	10100	200	10004	200	1	10000	100
10204	49956	10101	101	10000	100	10000	300	887777	10100	200	10004	200	1	10000	100
10204	49956	10101	101	10000	100	10000	300	887777	10100	200	10004	200	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.9956

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10024	49956	10011	11	10000	10	10000	30	887777	10010	20	10004	20	1	10000	10
10024	49956	10011	11	10000	10	10000	30	887777	10010	20	10000	20	1	10000	10
10024	49956	10011	11	10000	10	10000	30	887777	10010	20	10000	20	1	10000	10
10024	49956	10011	11	10000	10	10000	30	887777	10010	20	10000	20	1	10000	10
10024	49956	10011	11	10000	10	10000	30	887777	10010	20	10000	20	1	10000	10
10024	49956	10011	11	10000	10	10021	30	886604	10031	20	10034	20	1	10000	10
10024	49956	10011	11	10000	10	10000	30	887777	10010	20	10000	20	1	10000	10
10024	49956	10011	11	10000	10	10000	30	887777	10010	20	10000	20	1	10000	10
10024	49956	10011	11	10000	10	10000	30	887777	10010	20	10000	20	1	10000	10
10024	49956	10011	11	10000	10	10000	30	887777	10010	20	10004	20	1	10000	10