Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CBZ (taken)

Test 1: uops

Code:

  cbz x0, .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)
1004	4951	3326	3326	4317	11379	3793	4371	1076	1
1004	667	1001	1001	1000	3000	1000	1000	1000	1
1004	612	1001	1001	1000	3000	1000	1000	1000	1
1004	612	1001	1001	1000	3000	1000	1000	1000	1
1004	612	1001	1001	1000	3000	1000	1000	1000	1
1004	612	1001	1001	1000	3000	1000	1000	1000	1
1004	612	1001	1001	1000	3000	1000	1000	1000	1
1004	612	1001	1001	1000	3000	1000	1000	1000	1
1004	612	1001	1001	1000	3000	1000	1000	1000	1
1004	612	1001	1001	1000	3000	1000	1000	1000	1

Test 2: throughput

Count: 8

Code:

  cbz x0, .+4
  cbz x0, .+4
  cbz x0, .+4
  cbz x0, .+4
  cbz x0, .+4
  cbz x0, .+4
  cbz x0, .+4
  cbz x0, .+4

Initialization

  mov x0, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0615

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	93828	82852	82852	83986	240330	80110	80210	80206	1	100
80204	85016	80105	80105	80106	240318	80106	80206	80206	1	100
80204	84948	80105	80105	80106	240318	80106	80206	80264	1	100
80204	84349	80105	80105	80106	240318	80106	80206	80206	1	100
80204	84927	80105	80105	80106	240318	80106	80206	80206	1	100
80204	84915	80105	80105	80106	240318	80106	80206	80206	1	100
80204	84921	80105	80105	80106	240318	80106	80206	80206	1	100
80204	84921	80105	80105	80106	240318	80106	80206	80259	1	100
80204	84443	80105	80105	80106	240318	80106	80206	80206	1	100
80205	85154	80142	80142	80149	240318	80106	80206	80206	1	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 3.9638

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80025	367907	116322	116322	129615	240312	80104	80114	80021	1	10
80025	316851	80018	80018	80018	240059	80020	80030	80021	1	10
80024	316903	80012	80012	80011	240033	80011	80021	80021	1	10
80024	316868	80012	80012	80011	240077	80026	80036	80021	1	10
80024	316850	80012	80012	80011	240033	80011	80021	80021	1	10
80024	316845	80012	80012	80011	240050	80017	80027	80021	1	10
80024	316844	80012	80012	80011	240033	80011	80021	80021	1	10
80024	316843	80012	80012	80011	240056	80019	80029	80021	1	10
80024	316844	80012	80012	80011	240033	80011	80021	80021	1	10
80025	316847	80016	80016	80016	240033	80011	80021	80021	1	10