Icestorm: MVN (register, lsr, 64-bit) measurements

Code:

  mvn x0, x0, lsr #17

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000

Test 2: Latency 1->2

Code:

  mvn x0, x0, lsr #17

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10204	20030	20101	20101	0	0	10104	0	529100	10104	10210	10210	0	20001	0	0	10100
10204	20030	20101	20101	0	0	10104	0	529186	10104	10212	10212	0	20001	0	0	10100
10204	20030	20101	20101	0	0	10104	0	529083	10104	10212	10210	0	20001	0	0	10100
10204	20030	20101	20101	0	0	10104	0	529143	10104	10210	10212	0	20001	0	0	10100
10204	20030	20101	20101	0	0	10104	0	529186	10104	10212	10212	0	20001	0	0	10100
10204	20030	20101	20101	0	0	10104	0	529186	10104	10212	10212	0	20001	0	0	10100
10204	20030	20101	20101	0	0	10104	0	529186	10104	10212	10648	326	20190	118	1	10317
10204	20030	20101	20101	0	0	10104	0	529186	10104	10212	10212	0	20001	0	0	10100
10204	20030	20101	20101	0	0	10104	0	529186	10104	10212	10212	0	20001	0	0	10100
30895	69699	45256	38391	251	6614	25281	300	529186	10104	10212	10212	0	20001	0	0	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10024	20030	20021	20021	10025	0	529253	0	0	10020	10020	0	0	10020	0	0	20011	0	0	10010
10024	20030	20021	20021	10020	0	529253	0	0	10020	10020	0	0	10020	0	0	20011	0	0	10010
10024	20030	20021	20021	10020	0	529253	0	0	10020	10020	0	0	10020	0	0	20011	0	0	10010
10024	20030	20021	20021	10020	0	529253	0	0	10020	10020	0	0	10020	0	0	20011	0	0	10010
10024	20030	20021	20021	10020	0	529253	0	0	10020	10020	0	0	10020	0	0	20011	0	0	10010
10024	20030	20021	20021	10020	0	529253	0	0	10020	10020	0	0	10020	0	0	20011	0	0	10010
10024	20030	20021	20021	10020	0	529253	0	0	10020	10020	0	0	10020	0	0	20011	0	0	10010
10025	20060	20035	20035	10053	0	529253	0	0	10020	10020	0	0	10020	0	0	20011	0	0	10010
10024	20030	20021	20021	10020	0	529253	0	0	10020	10020	0	0	10020	0	0	20011	0	0	10010
10024	20030	20021	20021	10020	0	529253	0	0	10020	10020	0	0	10020	0	0	20011	0	0	10010

Test 3: throughput

Count: 8

Code:

  mvn x0, x8, lsr #17
  mvn x1, x8, lsr #17
  mvn x2, x8, lsr #17
  mvn x3, x8, lsr #17
  mvn x4, x8, lsr #17
  mvn x5, x8, lsr #17
  mvn x6, x8, lsr #17
  mvn x7, x8, lsr #17

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80204	53420	160116	160116	80129	1360838	80130	80234	80236	0	160016	0	80100
80204	53404	160117	160117	80130	1360838	80130	80236	80236	0	160017	0	80100
80204	53404	160117	160117	80130	1360838	80130	80236	80236	0	160017	0	80100
80204	53404	160117	160117	80130	1360838	80130	80236	80236	0	160017	0	80100
80204	53404	160117	160117	80130	1360838	80130	80236	80236	0	160017	0	80100
80204	53404	160117	160117	80130	1360838	80130	80236	80236	0	160017	0	80100
80204	53404	160117	160117	80130	1360838	80130	80236	80236	0	160017	0	80100
80204	53404	160117	160117	80130	1360838	80130	80236	80236	0	160017	0	80100
80204	53404	160117	160117	80130	1360838	80130	80236	80236	0	160017	0	80100
80205	53434	160158	160158	80175	1360838	80130	80236	80236	0	160017	0	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6671

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	53390	160039	160039	80051	0	1359975	0	0	80051	80056	0	0	80020	160011	80010
80024	53371	160021	160021	80020	0	1359903	0	0	80020	80020	0	0	80020	160011	80010
80024	53371	160021	160021	80020	0	1359903	0	0	80020	80020	0	0	80020	160011	80010
80024	53371	160021	160021	80020	0	1359903	0	0	80020	80020	0	0	80020	160011	80010
80024	53371	160021	160021	80020	0	1359903	0	0	80020	80020	0	0	80020	160011	80010
80024	53371	160021	160021	80020	0	1359903	0	0	80020	80020	0	0	80020	160011	80010
80024	53371	160021	160021	80020	0	1359903	0	0	80020	80020	0	0	80020	160011	80010
80024	53371	160021	160021	80020	0	1359903	0	0	80020	80020	0	0	80020	160011	80010
80024	53371	160021	160021	80020	0	1359903	0	0	80020	80020	0	0	80020	160011	80010
80024	53371	160021	160021	80020	0	1359903	0	0	80020	80020	0	0	80020	160011	80010

MVN (register, lsr, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations