Icestorm: CSEL (32-bit) measurements

Code:

  csel w0, w0, w1, hi

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	1030	1001	1001	1000	25603	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	3000	1001	1000

Test 2: Latency 1->2

Code:

  csel w0, w0, w1, hi

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10101	10101	10107	259057	10108	10214	30242	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30239	10001	10100
10204	10030	10101	10101	10107	259435	10107	10214	30242	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10028	259474	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010

Test 3: Latency 1->3

Code:

  csel w0, w1, w0, hi

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10101	10101	10108	259329	10107	10214	30242	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30380	10015	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10028	259528	10030	10038	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010

Test 4: Latency 1->4

Chain cycles: 1

Code:

  csel w0, w1, w2, hi
  tst x0, 1

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20201	20201	20209	519038	20209	20216	40232	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	40232	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	40232	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	40326	20115	10100
20204	20030	20201	20201	20211	519448	20208	20216	40232	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	40232	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	40232	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	40232	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	40232	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	40232	20101	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20021	20021	20028	519455	20029	20036	40020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	519956	20069	20080	40020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	40020	20011	10010

Test 5: throughput

Count: 8

Code:

  csel w0, w8, w9, hi
  csel w1, w8, w9, hi
  csel w2, w8, w9, hi
  csel w3, w8, w9, hi
  csel w4, w8, w9, hi
  csel w5, w8, w9, hi
  csel w6, w8, w9, hi
  csel w7, w8, w9, hi

Initialization

  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	26900	80115	80115	80120	291100	80120	80222	240263	80014	80100
80204	26742	80114	80114	80119	293236	80120	80221	240272	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	240272	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	240272	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	240272	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	240272	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	240272	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	240272	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	240272	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	240272	80015	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3340

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	27867	80038	80038	80052	304082	80020	80020	240020	80011	80010
80024	26791	80021	80021	80020	426780	80020	80020	240020	80011	80010
80024	26720	80021	80021	80020	426780	80020	80020	240020	80011	80010
80024	26719	80021	80021	80020	426780	80020	80020	240020	80011	80010
80024	26719	80021	80021	80020	426780	80020	80020	240020	80011	80010
80024	26719	80021	80021	80020	426780	80020	80020	240020	80011	80010
80024	26719	80021	80021	80020	426780	80020	80020	240020	80011	80010
80024	26719	80021	80021	80020	426780	80020	80020	240020	80011	80010
80024	26719	80021	80021	80020	426780	80020	80020	240020	80011	80010
80024	26719	80021	80021	80020	426780	80020	80020	240020	80011	80010

CSEL (32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations