Icestorm: RMIF measurements

Code:

  rmif x1, #1, #1

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001

Test 2: Latency 2->1

Chain cycles: 1

Code:

  rmif x1, #1, #1
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20107	519329	20107	20214	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010

Test 3: Latency 2->2

Code:

  rmif x0, #1, #1

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10205	10060	10215	10215	10246	254770	10208	10208	20228	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20228	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10098	10021	10021	10028	255150	10028	10032	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10

Test 4: throughput

Count: 8

Code:

  ands xzr, xzr, xzr
  rmif x0, #1, #1
  ands xzr, xzr, xzr
  rmif x0, #1, #1
  ands xzr, xzr, xzr
  rmif x0, #1, #1
  ands xzr, xzr, xzr
  rmif x0, #1, #1
  ands xzr, xzr, xzr
  rmif x0, #1, #1
  ands xzr, xzr, xzr
  rmif x0, #1, #1
  ands xzr, xzr, xzr
  rmif x0, #1, #1
  ands xzr, xzr, xzr
  rmif x0, #1, #1

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.7889

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
160204	63287	160112	160112	160118	689871	160124	160226	160218	160014	100
160204	63093	160114	160114	160118	686358	160118	160220	160220	160015	100
160204	63112	160112	160112	160118	690096	160121	160222	160220	160010	100
160204	63082	160112	160112	160118	688787	160118	160220	160220	160012	100
160204	63119	160113	160113	160117	689112	160123	160224	160220	160012	100
160204	63120	160113	160113	160117	692303	160120	160220	160220	160011	100
160204	63115	160112	160112	160118	688536	160118	160220	160220	160012	100
160204	63107	160112	160112	160118	688893	160120	160220	160220	160015	100
160204	63088	160112	160112	160118	690662	160118	160220	160220	160012	100
160204	63087	160111	160111	160115	691187	160118	160220	160220	160012	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.7880

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
160024	64470	160026	160026	160033	696238	160030	160040	160020	160001	10
160024	63254	160011	160011	160010	702015	160010	160020	160020	160001	10
160024	63104	160011	160011	160010	694347	160010	160020	160020	160001	10
160024	63078	160011	160011	160010	702621	160010	160020	160020	160001	10
160024	63022	160011	160011	160010	700861	160010	160020	160020	160001	10
160024	62993	160011	160011	160010	702571	160010	160020	160020	160001	10
160024	63059	160011	160011	160010	704553	160010	160020	160020	160001	10
160024	63030	160011	160011	160010	698890	160010	160020	160020	160001	10
160024	63009	160011	160011	160010	700698	160010	160020	160020	160001	10
160024	63030	160011	160011	160010	704553	160010	160020	160020	160001	10

Test 5: throughput

Count: 4

Code:

  fcmp s0, s0
  rmif x0, #1, #1
  rmif x0, #1, #1
  rmif x0, #1, #1
  rmif x0, #1, #1

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5998

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
50204	23999	50106	40104	10002	40111	10003	314903	40017	50116	40212	10004	80234	20010	40005	100
50204	23984	50106	40103	10003	40109	10003	315029	40018	50116	40212	10004	80282	20020	40033	100
50204	23969	50105	40102	10003	40112	10004	315987	40017	50116	40212	10004	80218	20006	40001	100
50204	23983	50104	40101	10003	40109	10003	315899	40077	50191	40272	10019	80218	20006	40001	100
50204	23966	50104	40101	10003	40109	10003	315563	40012	50112	40209	10003	80232	20008	40005	100
50204	23967	50104	40101	10003	40112	10004	315617	40017	50116	40212	10004	80218	20006	40003	100
50204	23966	50104	40101	10003	40109	10003	315563	40012	50112	40209	10003	80224	20008	40002	100
50204	23999	50105	40102	10003	40112	10004	315702	40012	50112	40209	10003	80218	20006	40001	100
50204	23979	50106	40103	10003	40109	10003	315520	40017	50116	40212	10004	80224	20008	40002	100
50204	24004	50106	40103	10003	40114	10004	315296	40012	50112	40209	10003	80224	20008	40001	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
50024	24151	50014	40012	10002	40022	10004	315977	40000	50010	40020	10000	80020	20000	40001	10
50024	23964	50011	40011	10000	40010	10000	316071	40045	50065	40064	10011	80020	20000	40001	10
50024	23977	50011	40011	10000	40010	10000	315614	40000	50010	40020	10000	80020	20000	40001	10
50024	23999	50011	40011	10000	40010	10000	315524	40000	50010	40020	10000	80020	20000	40001	10
50024	24004	50011	40011	10000	40010	10000	315828	40000	50010	40020	10000	80020	20000	40001	10
50024	23993	50011	40011	10000	40010	10000	315603	40000	50010	40020	10000	80020	20000	40001	10
50024	23986	50011	40011	10000	40010	10000	315747	40000	50010	40020	10000	80020	20000	40001	10
50024	23993	50011	40011	10000	40010	10000	316301	40000	50010	40020	10000	80020	20000	40001	10
50024	24296	50169	40138	10031	40137	10031	315602	40000	50010	40020	10000	80020	20000	40001	10
50024	24023	50011	40011	10000	40010	10000	315396	40000	50010	40020	10000	80020	20000	40001	10

Test 6: throughput

Count: 7

Code:

  ands xzr, xzr, xzr
  rmif x0, #1, #1
  rmif x0, #1, #1
  rmif x0, #1, #1
  rmif x0, #1, #1
  rmif x0, #1, #1
  rmif x0, #1, #1
  rmif x0, #1, #1

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5568

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	39011	80109	80109	80117	551078	80111	80212	140214	80005	100
80204	39035	80105	80105	80108	550486	80111	80212	140220	80004	100
80204	39032	80107	80107	80116	548963	80116	80216	140238	80015	100
80204	38941	80104	80104	80114	547262	80116	80216	140228	80004	100
80204	38989	80106	80106	80111	549465	80111	80212	140228	80005	100
80204	38950	80106	80106	80114	548458	80114	80216	140214	80004	100
80204	38985	80103	80103	80111	551999	80116	80216	140228	80006	100
80204	38914	80102	80102	80111	550000	80116	80216	140228	80007	100
80204	38958	80104	80104	80111	548033	80108	80208	140228	80007	100
80204	38942	80105	80105	80114	547687	80111	80212	140228	80004	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5561

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	39196	80031	80031	80042	549783	80036	80036	140020	80011	10
80024	38910	80021	80021	80020	551652	80020	80020	140020	80011	10
80024	38956	80021	80021	80020	551697	80020	80020	140020	80011	10
80024	39041	80021	80021	80020	549792	80020	80020	140020	80011	10
80024	38921	80021	80021	80020	551521	80020	80020	140020	80011	10
80024	38956	80021	80021	80020	549291	80020	80020	140020	80011	10
80024	38904	80021	80021	80020	549044	80020	80020	140020	80011	10
80024	38881	80021	80021	80020	549621	80020	80020	140020	80011	10
80024	38956	80021	80021	80020	550287	80020	80020	140020	80011	10
80024	38941	80021	80021	80020	549717	80020	80020	140124	80053	10

RMIF

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 2->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations