Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

MSUB (64-bit)

Test 1: uops

Code:

  msub x0, x0, x1, x2
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
100430301001100110002585610001000300010011000
100430301001100110002585610001000300010011000
100430301001100110002585610001000300010011000
100430301001100110002585610001000300010011000
100430301001100110002585610001000300010011000
100430301001100110002585610001000300010011000
100430301001100110002585610001000300010011000
100430301001100110002585610001000300010011000
100430301001100110002585610001000300010011000
100430301001100110002585610001000300010011000

Test 2: Latency 1->2

Code:

  msub x0, x0, x1, x2
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204300301010110101101002601501010010206302181000110100
10204300301010110101101002601561010010208302241000110100
10204300301010110101101002601501010010206302241000110100
10204300301010110101101002601561010010208302241000110100
10204300301010110101101002601561010010208302241000110100
10204300301010110101101002601561010010208302241000110100
10204300301010110101101002601561010010208302241000110100
10204300301010110101101002601561010010208302241000110100
10204300301010110101101002601561010010208302181000110100
10204300301010110101101002601501010010206302241000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
100243003010021100210100202600101003410050300891001610010
12102444201176311090673110562599071002010020300201001110010
100243003010021100210100202599161002010020300201001110010
100243003010021100210100202599161002010020300201001110010
100243003010021100210100202599161002010020300201001110010
100243003010021100210100202599161002010020300201001110010
100243003010021100210100202599161002010020300201001110010
100243003010021100210100202599161002010020300201001110010
100243003010021100210100202599161002010020300201001110010
100243003010021100210100202599161002010020300201001110010

Test 3: Latency 1->3

Code:

  msub x0, x1, x0, x2
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204300301010110101101002601441010010206302241000110100
10204300301010110101101002601561010010208302241000110100
10204300301010110101101002601561010010208302241000110100
10204300301010110101101002601561010010208302241000110100
10204300301010110101101002601561010010208302241000110100
10204300301010110101101002602591011410227302241000110100
10204300301010110101101002601561010010208302241000110100
10204300301010110101101002601561010010208302241000110100
10204300301010110101101002601561010010208302241000110100
10204300301010110101101002601561010010208302241000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024300301002110021100202599071002010020300201001110010
10024300301002110021100202599161002010020300201001110010
10024300301002110021100202599161002010020300201001110010
10024300301002110021100202599161002010020300201001110010
10024300301002110021100202599161002010020300201001110010
10024300301002110021100202599161002010020300201001110010
10024300301002110021100202599161002010020300201001110010
10024300301002110021100202599161002010020300201001110010
10024300301002110021100202599161002010020300201001110010
10024300301002110021100202599161002010020300201001110010

Test 4: Latency 1->4

Code:

  msub x0, x1, x2, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0034

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
1020410055101041010410105303151010510210302301000410100
1020410034101041010410105303151010510212302361000410100
1020410034101041010410105303151010510212302361000410100
1020410034101041010410105303151010510212302361000410100
1020410034101041010410105303151010510212302361000410100
1020410034101041010410105303151010510212302361000410100
1020410034101041010410105303151010510212302361000410100
1020410034101041010410105303151010510212302361000410100
1020510066101201012010124303151010510212302361000410100
1020410034101041010410105303151010510212302361000410100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0032

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
1002410035100251002510026300601002010020300201001110010
1002410032100211002110020300601002010020300201001110010
1002410032100211002110020300601002010020300201001110010
1002410032100211002110020300601002010020300201001110010
1002410032100211002110020300601002010020300201001110010
1002410032100211002110020300601002010020300201001110010
1002410032100211002110020300601002010020300201001110010
1002410032100211002110020300601002010020300201001110010
1002410032100211002110020300601002010020300201001110010
1002410032100211002110020300601002010020300201001110010

Test 5: throughput

Count: 8

Code:

  msub x0, x8, x9, x9
  msub x1, x8, x9, x9
  msub x2, x8, x9, x9
  msub x3, x8, x9, x9
  msub x4, x8, x9, x9
  msub x5, x8, x9, x9
  msub x6, x8, x9, x9
  msub x7, x8, x9, x9
  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
802048003480104801048010524031580105802122402368000480100
802048003480104801048010524031580105802122402368000480100
802048003480104801048010524031580105802122402368000480100
802048003480104801048010524036980124802362402368000480100
802048003480104801048010524031580105802122402368000480100
802048003480104801048010524031580105802122402368000480100
802048003480104801048010524031580105802122402368000480100
802048003480104801048010524031580105802122402368000480100
802048003480104801048010524031580105802122402368000480100
802048003480104801048010524031580105802122402368000480100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
800248005780025800250080026024006080020800202400208001180010
800248003280021800210080020024006080020800202400208001180010
800258006780041800410080045024006080020800202400208001180010
800248003280021800210080020024006080020800202400208001180010
800248003280021800210080020024006080020800202403178009980010
800258006780041800410080045024006080020800202401768005580010
800248003280021800210080020024012980043800462400208001180010
800248012680065800650080066024013280045800562400208001180010
800248003280021800210080020024012980043800442400208001180010
800248072980289802890080302024111380371804122409208027580010