Icestorm: UDIV (slow, 64-bit) measurements

Code:

  udiv x0, x1, x2

Initialization

  mov x1, #0xffffffffffffffff
  mov x2, #3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	21030	2001	2001	1000	187244	1000	1000	2000	2001	1000
1004	21030	2001	2001	1000	187244	1000	1000	2000	2001	1000
1004	21030	2001	2001	1000	187244	1000	1000	2000	2001	1000
1004	21030	2001	2001	1000	187244	1000	1000	2000	2001	1000
1004	21030	2001	2001	1000	187244	1000	1000	2000	2001	1000
1004	21030	2001	2001	1000	187415	1009	1016	2000	2001	1000
1004	21030	2001	2001	1000	187244	1000	1000	2000	2001	1000
1004	21030	2001	2001	1000	187244	1000	1000	2000	2001	1000
1004	21030	2001	2001	1000	187244	1000	1000	2000	2001	1000
1004	21030	2001	2001	1000	187244	1000	1000	2000	2001	1000

Test 2: Latency 1->2

Chain cycles: 2

Code:

  udiv x0, x1, x2
  eor x1, x1, x0
  eor x1, x1, x0

Initialization

  mov x1, #0xffffffffffffffff
  mov x2, #3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 21.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
30204	230030	40201	40201	30203	6177150	30203	30210	60220	40101	30100
30204	230030	40201	40201	30203	6177206	30203	30212	60224	40101	30100
30204	230030	40201	40201	30203	6177542	30232	30248	60224	40101	30100
30204	230030	40201	40201	30203	6177206	30203	30212	60224	40101	30100
30204	230030	40201	40201	30203	6177206	30203	30212	60224	40101	30100
30205	230060	40203	40203	30231	6177206	30203	30212	60224	40101	30100
30204	230030	40201	40201	30203	6177206	30203	30212	60224	40101	30100
30204	230030	40201	40201	30203	6177206	30203	30212	60296	40102	30100
30204	230030	40201	40201	30203	6177206	30203	30212	60224	40101	30100
30204	230030	40201	40201	30203	6177206	30203	30212	60224	40101	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 21.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
30024	230030	40011	40011	30013	6177434	30010	30020	60020	40001	30010
30024	230030	40011	40011	30010	6177829	30041	30068	60020	40001	30010
30024	230030	40011	40011	30010	6177465	30010	30020	60020	40001	30010
30024	230030	40011	40011	30010	6177465	30010	30020	60020	40001	30010
30025	230060	40012	40012	30040	6177465	30010	30020	60020	40001	30010
30024	230030	40011	40011	30010	6177465	30010	30020	60020	40001	30010
30024	230030	40011	40011	30010	6177465	30010	30020	60090	40002	30010
30024	230030	40011	40011	30010	6177465	30010	30020	60020	40001	30010
30024	230030	40011	40011	30010	6177465	30010	30020	60020	40001	30010
30024	230030	40011	40011	30010	6177816	30037	30057	60020	40001	30010

Test 3: Latency 1->3

Chain cycles: 2

Code:

  udiv x0, x1, x2
  eor x2, x2, x0
  eor x2, x2, x0

Initialization

  mov x1, #0xffffffffffffffff
  mov x2, #3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 21.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
30204	230030	40201	40201	30203	0	6177150	0	30203	30210	0	60224	40101	30100
30204	230030	40201	40201	30203	0	6177178	0	30203	30210	0	60224	40101	30100
30205	230060	40203	40203	30231	0	6177206	0	30203	30212	0	60224	40101	30100
30204	230030	40201	40201	30203	0	6177206	0	30203	30212	0	60224	40101	30100
30204	230030	40201	40201	30203	0	6177206	0	30203	30212	0	60224	40101	30100
30204	230030	40201	40201	30203	0	6177206	0	30203	30212	0	60224	40101	30100
30204	230030	40201	40201	30203	0	6177206	0	30203	30212	0	60296	40104	30100
30204	230030	40201	40201	30203	0	6177206	0	30203	30212	0	60224	40101	30100
30204	230030	40201	40201	30203	0	6177206	0	30203	30212	0	60224	40101	30100
30204	230030	40201	40201	30203	0	6177206	0	30203	30212	0	60224	40101	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 21.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
30024	230030	40011	40011	30013	0	6177484	0	30013	30032	0	60020	40001	30010
30024	230030	40011	40011	30010	0	6177465	0	30010	30020	0	60116	40004	30010
30024	230030	40011	40011	30010	0	6177465	0	30010	30020	0	60116	40003	30010
30025	230060	40012	40012	30037	0	6177465	0	30010	30020	0	60020	40001	30010
30024	230030	40011	40011	30010	0	6177815	0	30042	30070	0	60020	40001	30010
30024	230030	40011	40011	30010	0	6177465	0	30010	30020	0	60020	40001	30010
30024	230030	40011	40011	30010	0	6177465	0	30010	30020	0	60020	40001	30010
30025	230060	40012	40012	30040	0	6177829	0	30041	30068	0	60020	40001	30010
30024	230030	40011	40011	30010	0	6177465	0	30010	30020	0	60020	40001	30010
30024	230030	40011	40011	30010	0	6177465	0	30010	30020	0	60116	40004	30010

Test 4: throughput

Code:

  udiv x0, x1, x2

Initialization

  mov x1, #0xffffffffffffffff
  mov x2, #3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 21.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10204	210030	20101	20101	10100	1879544	10100	10206	20212	0	20001	0	0	10100
10204	210030	20101	20101	10100	1879544	10100	10208	20248	0	20002	0	0	10100
10204	210030	20101	20101	10100	1879544	10100	10208	20216	0	20001	0	0	10100
10204	210030	20101	20101	10100	1879544	10100	10208	20254	0	20003	0	0	10100
10204	210030	20101	20101	10100	1879544	10100	10208	20248	0	20002	0	0	10100
10204	210030	20101	20101	10100	1879544	10100	10208	20216	0	20001	0	0	10100
10204	210030	20101	20101	10100	1879544	10100	10208	20216	0	20001	0	0	10100
10204	210030	20101	20101	10100	1879544	10100	10208	20248	0	20002	0	0	10100
10204	210030	20101	20101	10100	1879544	10100	10208	20216	0	20001	0	0	10100
10204	210030	20101	20101	10100	1879544	10100	10208	20216	0	20001	0	0	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 21.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	210030	20021	20021	10020	0	1879304	0	10020	10028	0	20070	20012	10010
10024	210030	20021	20021	10020	0	1879304	0	10020	10020	0	20020	20011	10010
10024	210030	20021	20021	10020	0	1879304	0	10020	10020	0	20020	20011	10010
10024	210030	20021	20021	10020	0	1879304	0	10020	10020	0	20068	20012	10010
10024	210030	20021	20021	10020	0	1879304	0	10020	10020	0	20068	20012	10010
10024	210030	20021	20021	10020	0	1879304	0	10020	10020	0	20020	20011	10010
10024	210030	20021	20021	10020	0	1879304	0	10020	10020	0	20068	20012	10010
10024	210030	20021	20021	10020	0	1879304	0	10020	10020	0	20020	20011	10010
10024	210030	20021	20021	10020	0	1879304	0	10020	10020	0	20020	20011	10010
10024	210030	20021	20021	10020	0	1879421	0	10029	10044	0	20020	20011	10010

UDIV (slow, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations