Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
caspal x0, x1, x2, x3, [x6] nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0
(no loop instructions)
Retires (minus 70 nops): 6.000
Issues: 3.000
Integer unit issues: 0.001
Load/store unit issues: 3.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 76007 | 35182 | 3007 | 1 | 0 | 3006 | 0 | 0 | 3000 | 11000 | 3000 | 2000 | 4000 | 2000 | 7000 | 1 | 3000 | 3000 |
| 76004 | 34867 | 3001 | 1 | 0 | 3000 | 0 | 0 | 3000 | 11000 | 3000 | 2000 | 4000 | 2000 | 7000 | 1 | 3000 | 3000 |
| 76004 | 34471 | 3001 | 1 | 0 | 3000 | 0 | 0 | 3000 | 11000 | 3000 | 2000 | 4000 | 2000 | 7000 | 1 | 3000 | 3000 |
| 76004 | 34379 | 3001 | 1 | 0 | 3000 | 0 | 0 | 3000 | 11000 | 3000 | 2000 | 4000 | 2000 | 7000 | 1 | 3000 | 3000 |
| 76004 | 34494 | 3001 | 1 | 0 | 3000 | 0 | 0 | 3000 | 11000 | 3000 | 2000 | 4000 | 2000 | 7000 | 1 | 3000 | 3000 |
| 76004 | 34497 | 3001 | 1 | 0 | 3000 | 0 | 0 | 3000 | 11000 | 3000 | 2000 | 4000 | 2000 | 7000 | 1 | 3000 | 3000 |
| 76004 | 34414 | 3001 | 1 | 0 | 3000 | 0 | 0 | 3000 | 11001 | 3000 | 2000 | 4000 | 2000 | 7000 | 1 | 3000 | 3000 |
| 76004 | 34795 | 3001 | 1 | 0 | 3000 | 0 | 0 | 3000 | 11000 | 3000 | 2000 | 4000 | 2000 | 7000 | 1 | 3000 | 3000 |
| 76004 | 34493 | 3001 | 1 | 0 | 3000 | 0 | 0 | 3000 | 11000 | 3000 | 2000 | 4000 | 2000 | 7000 | 1 | 3000 | 3000 |
| 76004 | 34643 | 3001 | 1 | 0 | 3000 | 0 | 0 | 3000 | 11000 | 3000 | 2000 | 4000 | 2000 | 7000 | 1 | 3000 | 3000 |
Code:
caspal x0, x1, x2, x3, [x6] add x6, x6, 16
(fused SUBS/B.cc loop)
Result (median cycles for code): 19.0056
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 70234 | 191090 | 51280 | 21171 | 30109 | 21038 | 30003 | 68785 | 734719 | 52830 | 30202 | 40004 | 30202 | 70007 | 22736 | 30000 | 40100 |
| 70204 | 190061 | 52837 | 22836 | 30001 | 22827 | 30003 | 68785 | 734696 | 52830 | 30202 | 40004 | 30202 | 70007 | 22736 | 30000 | 40100 |
| 70205 | 190101 | 51293 | 21263 | 30030 | 21254 | 30003 | 68785 | 734696 | 52830 | 30202 | 40004 | 30202 | 70007 | 22736 | 30000 | 40100 |
| 70204 | 190056 | 52837 | 22836 | 30001 | 22827 | 30003 | 68785 | 734696 | 52830 | 30202 | 40004 | 30202 | 70007 | 22736 | 30000 | 40100 |
| 70204 | 190056 | 52837 | 22836 | 30001 | 22827 | 30003 | 68785 | 734696 | 52830 | 30202 | 40004 | 30202 | 70007 | 22736 | 30000 | 40100 |
| 70205 | 190100 | 52288 | 22258 | 30030 | 22249 | 30003 | 68785 | 734699 | 52830 | 30202 | 40004 | 30202 | 70007 | 22736 | 30000 | 40100 |
| 70204 | 190056 | 52837 | 22836 | 30001 | 22827 | 30036 | 68640 | 735092 | 52759 | 30235 | 40048 | 30202 | 70007 | 22736 | 30000 | 40100 |
| 70204 | 190056 | 52837 | 22836 | 30001 | 22827 | 30003 | 68785 | 734701 | 52830 | 30202 | 40004 | 30202 | 70007 | 22736 | 30000 | 40100 |
| 70205 | 190100 | 52193 | 22163 | 30030 | 22154 | 30003 | 68785 | 734697 | 52830 | 30202 | 40004 | 30202 | 70007 | 22736 | 30000 | 40100 |
| 70204 | 190059 | 52837 | 22836 | 30001 | 22827 | 30003 | 68785 | 734696 | 52830 | 30202 | 40004 | 30202 | 70007 | 22736 | 30000 | 40100 |
Result (median cycles for code): 19.0053
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 70054 | 191073 | 51189 | 21083 | 0 | 30106 | 20948 | 0 | 30003 | 68818 | 735008 | 52740 | 30022 | 40004 | 30022 | 70007 | 22734 | 30000 | 40010 |
| 70024 | 190122 | 52746 | 22746 | 0 | 30000 | 22737 | 0 | 30000 | 68463 | 734628 | 52737 | 30020 | 40000 | 30187 | 70392 | 22430 | 30000 | 40010 |
| 70024 | 190117 | 52749 | 22748 | 0 | 30001 | 22737 | 0 | 30003 | 68504 | 734861 | 52740 | 30022 | 40004 | 30022 | 70007 | 22734 | 30000 | 40010 |
| 70024 | 190091 | 52745 | 22744 | 0 | 30001 | 22737 | 0 | 30003 | 68485 | 734636 | 52740 | 30022 | 40004 | 30020 | 70000 | 22734 | 30000 | 40010 |
| 70025 | 190094 | 52671 | 22641 | 0 | 30030 | 22632 | 0 | 30000 | 68515 | 734679 | 52737 | 30020 | 40000 | 30152 | 70308 | 22811 | 30000 | 40010 |
| 70024 | 190053 | 52744 | 22744 | 0 | 30000 | 22737 | 0 | 30000 | 68477 | 734605 | 52737 | 30020 | 40000 | 30152 | 70308 | 22820 | 30000 | 40010 |
| 70024 | 190053 | 52744 | 22744 | 0 | 30000 | 22737 | 0 | 30000 | 68477 | 734606 | 52737 | 30020 | 40000 | 30020 | 70000 | 22734 | 30000 | 40010 |
| 70024 | 190463 | 52947 | 22831 | 0 | 30116 | 22824 | 0 | 30036 | 65032 | 734777 | 51601 | 30055 | 40048 | 30020 | 70000 | 22736 | 30000 | 40010 |
| 70024 | 190053 | 52744 | 22744 | 0 | 30000 | 22737 | 0 | 30132 | 69022 | 736557 | 52953 | 30152 | 40176 | 30020 | 70000 | 22734 | 30000 | 40010 |
| 70025 | 190099 | 51384 | 21354 | 0 | 30030 | 21347 | 0 | 30132 | 69388 | 736963 | 52956 | 30152 | 40176 | 30020 | 70000 | 22734 | 30000 | 40010 |
Code:
caspal x0, x1, x2, x3, [x6]
mov x7, 8
(fused SUBS/B.cc loop)
Result (median cycles for code): 30.0043
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 60209 | 300142 | 51996 | 21959 | 0 | 30037 | 11032 | 0 | 30024 | 3498592 | 3340416 | 0 | 42862 | 20216 | 40032 | 0 | 20216 | 70056 | 25460 | 30000 | 30102 |
| 60206 | 300043 | 55577 | 25560 | 0 | 30017 | 12838 | 0 | 30057 | 3063630 | 3341828 | 0 | 41323 | 20238 | 40076 | 0 | 20216 | 70056 | 25460 | 30000 | 30102 |
| 60206 | 300043 | 55577 | 25560 | 0 | 30017 | 12838 | 0 | 30024 | 3498616 | 3340460 | 0 | 42862 | 20216 | 40032 | 0 | 20216 | 70056 | 25460 | 30000 | 30102 |
| 60206 | 300043 | 55577 | 25560 | 0 | 30017 | 12838 | 0 | 30057 | 3165756 | 3341159 | 0 | 41695 | 20238 | 40076 | 0 | 20216 | 70056 | 25460 | 30000 | 30102 |
| 60206 | 300043 | 55577 | 25560 | 0 | 30017 | 12838 | 0 | 30024 | 3498616 | 3340460 | 0 | 42862 | 20216 | 40032 | 0 | 20216 | 70056 | 25460 | 30000 | 30102 |
| 60206 | 300043 | 55577 | 25560 | 0 | 30017 | 12838 | 0 | 30057 | 3283947 | 3341379 | 0 | 42127 | 20240 | 40076 | 0 | 20216 | 70056 | 25460 | 30000 | 30102 |
| 60206 | 300043 | 55577 | 25560 | 0 | 30017 | 12838 | 0 | 30024 | 3498616 | 3340460 | 0 | 42862 | 20216 | 40032 | 0 | 20216 | 70056 | 25460 | 30000 | 30102 |
| 60206 | 300043 | 55577 | 25560 | 0 | 30017 | 12838 | 0 | 30057 | 3398646 | 3340784 | 0 | 42541 | 20238 | 40076 | 0 | 20216 | 70056 | 25456 | 30000 | 30102 |
| 60206 | 300041 | 55573 | 25556 | 0 | 30017 | 12837 | 0 | 30024 | 3499103 | 3343963 | 0 | 42861 | 20216 | 40032 | 0 | 20216 | 70056 | 25456 | 30000 | 30102 |
| 60206 | 300041 | 55573 | 25556 | 0 | 30017 | 12837 | 0 | 30090 | 3084280 | 3342499 | 0 | 41440 | 20260 | 40120 | 0 | 20216 | 70056 | 25456 | 30000 | 30102 |
Result (median cycles for code): 30.0043
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) |
| 60029 | 300151 | 51913 | 21873 | 30040 | 10942 | 30021 | 3498322 | 3340512 | 42769 | 20034 | 40028 | 20034 | 70049 | 0 | 25460 | 30000 | 0 | 30012 |
| 60026 | 300043 | 55486 | 25470 | 30016 | 12748 | 30021 | 3498346 | 3340534 | 42769 | 20034 | 40028 | 20058 | 70133 | 0 | 24880 | 30000 | 0 | 30012 |
| 60026 | 300043 | 55486 | 25470 | 30016 | 12748 | 30075 | 3401420 | 3341259 | 42489 | 20070 | 40100 | 20034 | 70049 | 0 | 25460 | 30000 | 0 | 30012 |
| 60026 | 300043 | 55486 | 25470 | 30016 | 12748 | 30021 | 3498346 | 3340534 | 42769 | 20034 | 40028 | 20034 | 70049 | 0 | 25460 | 30000 | 0 | 30012 |
| 60027 | 300073 | 51929 | 21884 | 30045 | 10970 | 30021 | 3498346 | 3340534 | 42769 | 20034 | 40028 | 20034 | 70049 | 0 | 25460 | 30000 | 0 | 30012 |
| 60026 | 300043 | 55486 | 25470 | 30016 | 12748 | 30021 | 3498346 | 3340534 | 42769 | 20034 | 40028 | 20034 | 70049 | 0 | 25460 | 30000 | 0 | 30012 |
| 60028 | 300113 | 52806 | 22731 | 30075 | 11408 | 30021 | 3498346 | 3340534 | 42769 | 20034 | 40028 | 20034 | 70049 | 0 | 25460 | 30000 | 0 | 30012 |
| 60026 | 300043 | 55486 | 25470 | 30016 | 12748 | 30021 | 3498346 | 3340534 | 42769 | 20034 | 40028 | 20034 | 70049 | 0 | 25460 | 30000 | 0 | 30012 |
| 60029 | 300125 | 53575 | 23512 | 30063 | 11790 | 30021 | 3498346 | 3340534 | 42769 | 20034 | 40028 | 20034 | 70049 | 0 | 25460 | 30000 | 0 | 30012 |
| 60026 | 300043 | 55486 | 25470 | 30016 | 12748 | 30021 | 3498346 | 3340534 | 42769 | 20034 | 40028 | 20034 | 70049 | 0 | 25460 | 30000 | 0 | 30012 |