Icestorm: SDIV (fast, 64-bit) measurements

Code:

  sdiv x0, x1, x2

Initialization

  mov x1, #0
  mov x2, #0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	7030	2001	2001	1000	61748	1000	1000	2000	2001	1000
1004	7030	2001	2001	1000	61748	1000	1000	2000	2001	1000
1004	7030	2001	2001	1000	61748	1000	1000	2000	2001	1000
1004	7030	2001	2001	1000	61748	1000	1000	2000	2001	1000
1004	7030	2001	2001	1000	61748	1000	1000	2000	2001	1000
1004	7030	2001	2001	1000	61748	1000	1000	2000	2001	1000
1004	7030	2001	2001	1000	61748	1000	1000	2000	2001	1000
1004	7030	2001	2001	1000	61748	1000	1000	2000	2001	1000
1004	7030	2001	2001	1000	61748	1000	1000	2000	2001	1000
1004	7030	2001	2001	1000	61748	1000	1000	2000	2001	1000

Test 2: Latency 1->2

Chain cycles: 2

Code:

  sdiv x0, x1, x2
  eor x1, x1, x0
  eor x1, x1, x0

Initialization

  mov x1, #0
  mov x2, #0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 7.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
30204	90030	40201	40201	30203	2398634	30203	30210	60220	40101	30100
30204	90030	40201	40201	30203	2398718	30203	30212	60224	40101	30100
30205	90060	40206	40206	30233	2398718	30203	30212	60224	40101	30100
30204	90030	40201	40201	30203	2398718	30203	30212	60224	40101	30100
30204	90030	40201	40201	30203	2398718	30203	30212	60224	40101	30100
30204	90030	40201	40201	30203	2398718	30203	30212	60224	40101	30100
30204	90030	40201	40201	30203	2398718	30203	30212	60224	40101	30100
30204	90030	40201	40201	30203	2398718	30203	30212	60296	40106	30100
30204	90030	40201	40201	30203	2399075	30233	30252	60224	40101	30100
30204	90030	40201	40201	30203	2398718	30203	30212	60224	40101	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 7.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
30024	90030	40011	40011	30013	2398954	30013	30030	60020	40001	30010
30024	90030	40011	40011	30010	2398977	30010	30020	60020	40001	30010
30024	90030	40011	40011	30010	2398977	30010	30020	60020	40001	30010
30024	90030	40011	40011	30010	2398977	30010	30020	60020	40001	30010
30025	90060	40017	40017	30044	2398977	30010	30020	60020	40001	30010
30024	90030	40011	40011	30010	2398977	30010	30020	60020	40001	30010
30025	90060	40018	40018	30045	2398977	30010	30020	60020	40001	30010
30024	90030	40011	40011	30010	2398977	30010	30020	60020	40001	30010
30024	90030	40011	40011	30010	2400968	30137	30179	60020	40001	30010
30024	90030	40011	40011	30010	2398977	30010	30020	60020	40001	30010

Test 3: Latency 1->3

Chain cycles: 2

Code:

  sdiv x0, x1, x2
  eor x2, x2, x0
  eor x2, x2, x0

Initialization

  mov x1, #0
  mov x2, #0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 7.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
30205	90060	40209	40209	30236	2398636	30203	30210	60224	40101	30100
30204	90030	40201	40201	30203	2398718	30203	30212	60224	40101	30100
30204	90030	40201	40201	30203	2398718	30203	30213	60224	40101	30100
30204	90030	40201	40201	30203	2398718	30203	30212	60224	40101	30100
30204	90030	40201	40201	30203	2398718	30203	30212	60224	40101	30100
30204	90030	40201	40201	30203	2398718	30203	30212	60224	40101	30100
30204	90030	40201	40201	30203	2398718	30203	30212	60224	40101	30100
30204	90030	40201	40201	30203	2398718	30203	30212	60224	40101	30100
30204	90030	40201	40201	30203	2398718	30203	30212	60224	40101	30100
30204	90030	40201	40201	30203	2398718	30203	30212	60224	40101	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 7.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
30024	90030	40011	40011	30013	0	2398935	0	0	30010	30020	0	0	60020	40001	30010
30024	90030	40011	40011	30010	0	2398977	0	0	30010	30020	0	0	60020	40001	30010
30024	90030	40011	40011	30010	0	2398977	0	0	30010	30020	0	0	60020	40001	30010
30024	90030	40011	40011	30010	1416	2432229	24732	1193	32940	32244	1680	8	60020	40001	30010
30024	90030	40011	40011	30010	0	2398977	0	0	30010	30020	0	0	60020	40001	30010
30024	90030	40011	40011	30010	0	2398977	0	0	30010	30020	0	0	60020	40001	30010
30024	90030	40011	40011	30010	0	2398977	0	0	30010	30020	0	0	60020	40001	30010
30024	90030	40011	40011	30010	0	2398977	0	0	30010	30020	0	0	60020	40001	30010
30024	90030	40011	40011	30010	0	2398977	0	0	30010	30020	0	0	60020	40001	30010
30024	90030	40011	40011	30010	0	2398977	0	0	30010	30020	0	0	60130	40008	30010

Test 4: throughput

Code:

  sdiv x0, x1, x2

Initialization

  mov x1, #0
  mov x2, #0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	70030	20101	20101	10100	620048	10100	10206	20212	20001	10100
10205	70060	20105	20105	10110	620048	10100	10208	20216	20001	10100
10204	70030	20101	20101	10100	620048	10100	10208	20216	20001	10100
10204	70030	20101	20101	10100	620048	10100	10208	20216	20001	10100
10204	70030	20101	20101	10100	620048	10100	10208	20216	20001	10100
10204	70030	20101	20101	10100	620048	10100	10208	20216	20001	10100
10204	70030	20101	20101	10100	620048	10100	10208	20216	20001	10100
10205	70060	20105	20105	10110	620048	10100	10208	20216	20001	10100
10204	70030	20101	20101	10100	620048	10100	10208	20216	20001	10100
10205	70060	20105	20105	10110	620048	10100	10208	20216	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	70030	20021	20021	10020	619808	10020	10020	20068	20015	10010
10024	70030	20021	20021	10020	619808	10020	10020	20020	20011	10010
10024	70030	20021	20021	10020	619808	10020	10020	20020	20011	10010
10024	70030	20021	20021	10020	619808	10020	10020	20020	20011	10010
10024	70030	20021	20021	10020	619808	10020	10020	20020	20011	10010
10024	70030	20021	20021	10020	619808	10020	10020	20020	20011	10010
10024	70030	20021	20021	10020	619808	10020	10020	20020	20011	10010
10024	70030	20021	20021	10020	619808	10020	10020	20020	20011	10010
10024	70030	20021	20021	10020	619808	10020	10020	20068	20015	10010
10024	70030	20021	20021	10020	619808	10020	10020	20020	20011	10010

SDIV (fast, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations