Icestorm: ADC (32-bit) measurements

Code:

  adc w0, w0, w1

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	1030	1001	1001	1000	25603	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	3000	1001	1000

Test 2: Latency 1->2

Code:

  adc w0, w0, w1

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10101	10101	10108	259434	10107	10214	30242	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100
10204	10030	10101	10101	10107	259539	10107	10213	30242	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10024	10030	10021	10021	10028	259474	10020	10020	30020	0	0	10011	0	0	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	0	0	10011	0	0	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	0	0	10011	0	0	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	0	0	10011	0	0	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	0	0	10011	0	0	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	0	0	10011	0	0	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	0	0	10011	0	0	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	0	0	10011	0	0	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	0	0	10011	0	0	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	0	0	10011	0	0	10010

Test 3: Latency 1->3

Code:

  adc w0, w1, w0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10101	10101	10108	259416	10107	10214	30242	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30242	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10028	259474	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010

Test 4: Latency 1->4

Chain cycles: 1

Code:

  adc w0, w1, w2
  tst x0, 1

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20178	20201	20201	20210	519039	20211	20216	40232	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	40232	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	40232	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	40232	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	40232	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	40232	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	40232	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	40232	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	40232	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	40232	20101	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20021	20021	20028	519358	20029	20036	40020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	40020	20011	10010
20025	20060	20035	20035	20069	519591	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	40020	20011	10010

Test 5: throughput

Count: 8

Code:

  adc w0, w8, w9
  adc w1, w8, w9
  adc w2, w8, w9
  adc w3, w8, w9
  adc w4, w8, w9
  adc w5, w8, w9
  adc w6, w8, w9
  adc w7, w8, w9

Initialization

  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	26883	80115	80115	80120	292168	80120	80222	240266	80015	80100
80204	26752	80115	80115	80120	293236	80120	80224	240272	80015	80100
80204	26743	80115	80115	80120	293236	80120	80224	240272	80015	80100
80204	26737	80115	80115	80120	284482	80174	80280	240272	80015	80100
80204	26741	80115	80115	80120	293236	80120	80224	240272	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	240272	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	240272	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	240272	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	240272	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	240272	80015	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3340

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80024	28000	80038	80038	80051	389437	80020	80020	240020	0	80011	0	0	80010
80024	26772	80021	80021	80020	426780	80020	80020	240020	0	80011	0	0	80010
80024	26727	80021	80021	80020	426780	80020	80020	240020	0	80011	0	0	80010
80024	26723	80021	80021	80020	426780	80020	80020	240020	0	80011	0	0	80010
80024	26723	80021	80021	80020	426780	80020	80020	240020	0	80011	0	0	80010
80024	26723	80021	80021	80020	426780	80020	80020	240020	0	80011	0	0	80010
80024	26723	80021	80021	80020	426780	80020	80020	240020	0	80011	0	0	80010
80024	26892	80021	80021	80020	389437	80020	80020	240020	0	80011	0	0	80010
80024	26723	80021	80021	80020	426780	80020	80020	240020	0	80011	0	0	80010
80024	27575	80038	80038	80054	426780	80020	80020	240020	0	80011	0	0	80010

ADC (32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations