Icestorm: LDURB measurements

Code:

  ldurb w0, [x6, #1]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	673	1027	1	1026	1000	8238	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	1000	1	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldurb w0, [x6, #1]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70154	40108	30107	10001	30130	10003	1859581	694063	40106	30212	10004	60294	10017	30009	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859392	693993	40106	30212	10004	60224	10004	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	10004	30002	10000	30100
40204	70041	40102	30102	10000	30103	10015	1859737	694106	40150	30247	10017	60224	10004	30003	10000	30100
40204	70132	40104	30104	10000	30103	10003	1859398	693968	40106	30212	10004	60224	10004	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	10004	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	10004	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	10004	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	10004	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	10004	30002	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
40025	70150	40018	30017	10001	30040	10003	1859623	694693	40016	30032	10004	60044	10004	0	30003	10000	0	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	0	30003	10000	0	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	0	30003	10000	0	30010
40024	70047	40013	30013	10000	30010	10015	1860016	694855	40060	30071	10017	60020	10000	0	30003	10000	0	30010
40024	70047	40013	30013	10000	30010	10015	1861672	695527	40060	30071	10017	60020	10000	0	30003	10000	0	30010
40024	70054	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	0	30003	10000	0	30010
40024	70050	40013	30013	10000	30010	10000	1859679	694725	40010	30020	10000	60020	10000	0	30003	10000	0	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	0	30003	10000	0	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	0	30003	10000	0	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	0	30003	10000	0	30010

Test 3: throughput

Count: 8

Code:

  ldurb w0, [x6, #1]
  ldurb w0, [x6, #1]
  ldurb w0, [x6, #1]
  ldurb w0, [x6, #1]
  ldurb w0, [x6, #1]
  ldurb w0, [x6, #1]
  ldurb w0, [x6, #1]
  ldurb w0, [x6, #1]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40175	80121	101	80020	100	80008	300	637738	80108	200	80012	200	80012	1	80000	100
80204	40066	80101	101	80000	100	80056	307	389584	80158	202	80067	200	80012	1	80000	100
80204	40177	80131	101	80030	100	80059	300	640828	80159	200	80071	200	80012	1	80000	100
80204	40053	80101	101	80000	100	80008	300	640286	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640070	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640070	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640070	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640070	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640070	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640070	80108	200	80012	200	80012	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40216	80039	11	80028	10	80059	30	326119	80069	20	80071	20	80012	1	80000	10
80024	40064	80011	11	80000	10	80000	30	640526	80010	20	80000	20	80000	1	80000	10
80024	40102	80011	11	80000	10	80192	30	584264	80202	20	80228	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	80010	20	80000	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	80010	20	80000	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	641912	80010	20	80000	20	80000	1	80000	10
80024	40071	80011	11	80000	10	80000	30	640310	80010	20	80000	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	80010	20	80000	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	80010	20	80000	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	80010	20	80000	20	80000	1	80000	10

LDURB

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations