Icestorm: LDRH (register, sxtw) measurements

Code:

  ldrh w0, [x6, w7, sxtw]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	680	1023	1	1022	1000	8166	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	2000	1	1000
1004	554	1001	1	1000	1000	8166	1000	1000	2000	1	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrh w0, [x6, w7, sxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70168	40108	30107	10001	30130	10003	1859581	694063	40106	30212	10004	60220	20008	30003	10000	30100
40205	70163	40112	30110	10002	30135	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859662	694096	40106	30212	10004	60224	20008	30003	10000	30100
40204	70048	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1861984	695042	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70058	40103	30103	10000	30103	10003	1859797	694151	40106	30212	10004	60224	20008	30003	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40026	70549	40026	30023	10003	30072	10003	1859947	693828	40016	30030	10004	60098	20026	30012	10000	30010
40024	70061	40012	30012	10000	30010	10000	1859652	694714	40010	30020	10000	60020	20000	30003	10000	30010
40024	70040	40012	30012	10000	30010	10000	1860516	695066	40010	30020	10000	60020	20000	30003	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859733	694747	40010	30020	10000	60020	20000	30003	10000	30010
40024	70422	40060	30048	10012	30142	10000	1859652	694714	40010	30020	10000	60122	20034	30011	10000	30010
40024	70043	40012	30012	10000	30010	10004	1861426	730376	40017	30032	10005	60020	20000	30003	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859652	694714	40010	30020	10000	60020	20000	30003	10000	30010
40024	70044	40012	30012	10000	30010	10000	1860408	695022	40010	30020	10000	60328	20104	30039	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859652	694714	40010	30020	10000	60020	20000	30003	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859652	694714	40010	30020	10000	60020	20000	30003	10000	30010

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrh w0, [x6, w7, sxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70150	40108	30107	10001	30130	10003	1859350	693826	40106	30210	10004	60220	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60302	20034	30008	10000	30100
40204	70048	40102	30102	10000	30103	10003	1859581	694068	40106	30212	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859608	694078	40106	30212	10004	60224	20008	30002	10000	30100
40205	70072	40110	30108	10002	30135	10003	1859905	694199	40106	30212	10004	60224	20008	30003	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70156	40018	30017	10001	30040	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70053	40013	30013	10000	30010	10004	1859671	729653	40017	30032	10005	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	20000	30003	10000	30010

Test 4: throughput

Count: 8

Code:

  ldrh w0, [x6, w7, sxtw]
  ldrh w0, [x6, w7, sxtw]
  ldrh w0, [x6, w7, sxtw]
  ldrh w0, [x6, w7, sxtw]
  ldrh w0, [x6, w7, sxtw]
  ldrh w0, [x6, w7, sxtw]
  ldrh w0, [x6, w7, sxtw]
  ldrh w0, [x6, w7, sxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40296	80137	101	0	80036	100	0	80008	300	248262	80108	200	80012	200	160028	1	80000	100
80204	40050	80101	101	0	80000	100	0	80008	300	640250	80108	200	80012	200	160024	1	80000	100
80204	40049	80101	101	0	80000	100	0	80008	300	640142	80108	200	80012	200	160024	1	80000	100
80204	40049	80101	101	0	80000	100	0	80008	300	640142	80108	200	80012	200	160024	1	80000	100
80204	40049	80101	101	0	80000	100	0	80008	300	640142	80108	200	80012	200	160024	1	80000	100
80204	40049	80101	101	0	80000	100	0	80008	300	640142	80108	200	80012	200	160024	1	80000	100
80204	40049	80101	101	0	80000	100	0	80008	300	640142	80108	200	80012	200	160024	1	80000	100
80204	40049	80101	101	0	80000	100	0	80008	300	640142	80108	200	80012	200	160024	1	80000	100
80204	40049	80101	101	0	80000	100	0	80008	300	640142	80108	200	80012	200	160024	1	80000	100
80204	40049	80101	101	0	80000	100	0	80008	300	640142	80108	200	80012	200	160024	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40271	80041	11	80030	10	80008	30	320262	80018	20	80012	20	160000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640112	80010	20	80000	20	160000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	160000	1	80000	10
80024	40047	80011	11	80000	10	80057	30	342891	80067	20	80069	20	160000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640220	80010	20	80000	20	160000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	160000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	160000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	160000	1	80000	10
80024	40053	80011	11	80000	10	80000	30	640274	80010	20	80000	20	160000	1	80000	10
80024	40066	80011	11	80000	10	80000	30	640220	80010	20	80000	20	160000	1	80000	10

LDRH (register, sxtw)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations