Icestorm: NEGS (register, 64-bit) measurements

Code:

  negs x0, x0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	1030	1001	1001	1000	25043	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	1000	1001	1000

Test 2: Latency 1->2

Code:

  negs x0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10101	10101	10108	0	251647	0	0	10109	10210	0	0	10208	10001	10100
10204	10030	10101	10101	10108	0	251660	0	0	10106	10206	0	0	10208	10001	10100
10204	10030	10101	10101	10108	0	251774	0	0	10108	10208	0	0	10208	10001	10100
10204	10030	10101	10101	10108	0	251774	0	0	10108	10208	0	0	10208	10001	10100
10204	10030	10101	10101	10108	0	251205	0	0	10109	10209	0	0	10208	10001	10100
10204	10030	10101	10101	10108	0	251774	0	0	10108	10208	0	0	10208	10001	10100
10204	10030	10101	10101	10108	0	251774	0	0	10108	10208	0	0	10208	10001	10100
10204	10030	10101	10101	10108	0	251774	0	0	10108	10208	0	0	10208	10001	10100
10204	10030	10101	10101	10108	0	251774	0	0	10108	10208	0	0	10208	10001	10100
10204	10030	10101	10101	10108	0	251774	0	0	10108	10208	0	0	10208	10001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10028	253256	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	254627	10136	10136	10020	10011	10010

Test 3: Latency 3->2

Chain cycles: 1

Code:

  negs x0, x1
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20108	519312	20107	20212	20212	20001	20100
20204	20030	20101	20101	20107	519416	20107	20212	20216	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	20100
20205	20060	20115	20115	20148	519548	20108	20216	20216	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	20100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	0	0	20018	0	519507	20017	20032	20020	20001	20010
20024	20030	20011	20011	0	0	20010	0	519598	20010	20020	20020	20001	20010
20024	20030	20011	20011	0	0	20010	0	519598	20010	20020	20020	20001	20010
20024	20030	20011	20011	0	0	20010	0	519598	20010	20020	20020	20001	20010
20024	20030	20011	20011	0	0	20010	0	519598	20010	20020	20020	20001	20010
20024	20030	20011	20011	0	0	20010	0	519598	20010	20020	20020	20001	20010
20024	20030	20011	20011	0	0	20010	0	519598	20010	20020	20020	20001	20010
20024	20030	20011	20011	0	0	20010	0	519598	20010	20020	20020	20001	20010
20024	20030	20011	20011	0	0	20010	0	519598	20010	20020	20020	20001	20010
20024	20030	20011	20011	0	0	20010	0	519598	20010	20020	20020	20001	20010

Test 4: throughput

Count: 8

Code:

  negs x0, x8
  negs x1, x8
  negs x2, x8
  negs x3, x8
  negs x4, x8
  negs x5, x8
  negs x6, x8
  negs x7, x8

Initialization

  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5010

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	40104	80110	80110	0	0	80113	0	240345	80115	80216	80216	80012	80100
80204	40081	80112	80112	0	0	80115	0	240345	80115	80216	80216	80012	80100
80204	40081	80112	80112	0	0	80115	0	240444	80148	80248	80216	80012	80100
80205	40106	80143	80143	0	0	80151	0	240345	80115	80216	80246	80043	80100
80204	40081	80112	80112	0	0	80115	0	240342	80114	80214	80216	80012	80100
80205	40106	80141	80141	0	0	80145	0	240436	80147	80248	80216	80012	80100
80204	40081	80112	80112	0	0	80115	0	240345	80115	80216	80216	80012	80100
80204	40081	80112	80112	0	0	80115	0	240345	80115	80216	80251	80042	80100
80205	40106	80143	80143	0	0	80151	0	240345	80115	80216	80216	80012	80100
80204	40081	80112	80112	0	0	80115	0	240345	80115	80216	80216	80012	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80024	40070	80031	80031	80034	240108	80034	80034	80069	0	0	80054	0	0	80010
80024	40030	80021	80021	80020	240065	80020	80020	80020	0	0	80011	0	0	80010
80024	40030	80021	80021	80020	240065	80020	80020	80020	0	0	80011	0	0	80010
80024	40030	80021	80021	80020	240065	80020	80020	80020	0	0	80011	0	0	80010
80024	40030	80021	80021	80020	240065	80020	80020	80020	0	0	80011	0	0	80010
80024	40030	80021	80021	80020	240065	80020	80020	80020	0	0	80011	0	0	80010
80024	40030	80021	80021	80020	240065	80020	80020	80020	0	0	80011	0	0	80010
80024	40030	80021	80021	80020	240065	80020	80020	80020	0	0	80011	0	0	80010
80024	40030	80021	80021	80020	240065	80020	80020	80020	0	0	80011	0	0	80010
80024	40030	80021	80021	80020	240065	80020	80020	80020	0	0	80011	0	0	80010

NEGS (register, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 3->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations