Icestorm: NGC (register, 64-bit) measurements

Code:

  ngc x0, x0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	1030	1001	1001	1000	25603	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	2000	1001	1000
1004	1073	1001	1001	1000	25603	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	2000	1001	1000

Test 2: Latency 1->2

Code:

  ngc x0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10101	10101	10107	259329	10107	10214	20228	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259857	10147	10260	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10029	259474	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010

Test 3: Latency 1->3

Chain cycles: 1

Code:

  ngc x0, x1
  tst x0, 1

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20201	20201	20209	519211	20210	20216	30224	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	30224	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	30224	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	30224	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	30224	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	30224	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	30224	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	30224	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	30224	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	30224	20101	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20021	20021	0	0	20028	0	519455	20020	20020	30020	20011	10010
20024	20030	20021	20021	0	0	20020	0	519591	20020	20020	30113	20025	10010
20024	20030	20021	20021	0	0	20020	0	519591	20020	20020	30020	20011	10010
20024	20030	20021	20021	0	0	20020	0	519591	20020	20020	30020	20011	10010
20024	20030	20021	20021	0	0	20020	0	519591	20020	20020	30020	20011	10010
20024	20030	20021	20021	0	0	20020	0	519591	20020	20020	30020	20011	10010
20024	20030	20021	20021	0	0	20020	0	519591	20020	20020	30020	20011	10010
20024	20030	20021	20021	0	0	20020	0	519591	20020	20020	30020	20011	10010
20024	20030	20021	20021	0	0	20020	0	519591	20020	20020	30020	20011	10010
20024	20030	20021	20021	0	0	20020	0	519591	20020	20020	30020	20011	10010

Test 4: throughput

Count: 8

Code:

  ngc x0, x8
  ngc x1, x8
  ngc x2, x8
  ngc x3, x8
  ngc x4, x8
  ngc x5, x8
  ngc x6, x8
  ngc x7, x8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	26865	80114	80114	80119	292168	80120	80224	160360	80058	80100
80204	26747	80115	80115	80120	293236	80120	80224	160248	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	160248	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	160248	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	160248	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	160248	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	160248	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	160248	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	160248	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	160248	80015	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3340

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	27933	80038	80038	80052	333593	80051	80052	160020	80011	80010
80024	26821	80021	80021	80020	389437	80020	80020	160020	80011	80010
80024	26718	80021	80021	80020	389437	80020	80020	160020	80011	80010
80024	26718	80021	80021	80020	389437	80020	80020	160020	80011	80010
80024	26727	80021	80021	80020	389437	80020	80020	160020	80011	80010
80024	26718	80021	80021	80020	357610	80052	80056	160020	80011	80010
80024	26729	80021	80021	80020	389437	80020	80020	160020	80011	80010
80024	26726	80021	80021	80020	389437	80020	80020	160020	80011	80010
80024	26722	80021	80021	80020	389437	80020	80020	160020	80011	80010
80024	26722	80021	80021	80020	389437	80020	80020	160020	80011	80010

NGC (register, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations