Icestorm: SETF8 measurements

Code:

  setf8 w1

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001

Test 2: Latency 2->1

Chain cycles: 1

Code:

  setf8 w1
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20108	519339	20108	20216	30221	20001	10100
20204	20030	20101	20101	20108	519434	20107	20214	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20205	20060	20115	20115	20147	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519638	20018	20036	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20018	519495	20018	20036	30038	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010

Test 3: Latency 2->2

Code:

  setf8 w0

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10201	10201	10209	254709	10208	10208	20228	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100
10205	10060	10215	10215	10250	254709	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10029	255236	10029	10032	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20174	10053	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255593	10059	10059	20098	10032	10

Test 4: throughput

Count: 8

Code:

  ands xzr, xzr, xzr
  setf8 w0
  ands xzr, xzr, xzr
  setf8 w0
  ands xzr, xzr, xzr
  setf8 w0
  ands xzr, xzr, xzr
  setf8 w0
  ands xzr, xzr, xzr
  setf8 w0
  ands xzr, xzr, xzr
  setf8 w0
  ands xzr, xzr, xzr
  setf8 w0
  ands xzr, xzr, xzr
  setf8 w0

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.7890

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
160204	63345	160115	160115	160120	681658	160309	160409	160222	160013	100
160204	63138	160113	160113	160119	687412	160121	160222	160226	160019	100
160204	63102	160113	160113	160118	686775	160119	160220	160216	160011	100
160204	63065	160115	160115	160120	688894	160118	160220	160216	160008	100
160204	63147	160112	160112	160118	691935	160118	160220	160220	160011	100
160204	63170	160112	160112	160118	690544	160123	160224	160224	160014	100
160204	63099	160111	160111	160116	689652	160118	160220	160216	160011	100
160204	63102	160120	160120	160126	688283	160118	160220	160220	160013	100
160204	63108	160112	160112	160118	688787	160118	160220	160220	160015	100
160204	63091	160114	160114	160120	687081	160120	160220	160220	160012	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.7882

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
160024	64470	160026	160026	160033	698935	160033	160044	160020	160001	10
160024	63239	160011	160011	160010	695853	160010	160020	160020	160001	10
160024	63096	160011	160011	160010	698154	160010	160020	160020	160001	10
160024	63032	160011	160011	160010	700418	160010	160020	160020	160001	10
160024	63179	160011	160011	160010	703270	160010	160020	160020	160001	10
160024	63066	160011	160011	160010	699082	160010	160020	160020	160001	10
160024	63044	160011	160011	160010	705830	160010	160020	160020	160001	10
160024	63042	160011	160011	160010	701109	160010	160020	160020	160001	10
160024	63060	160011	160011	160010	697346	160010	160020	160020	160001	10
160024	63072	160011	160011	160010	698468	160010	160020	160020	160001	10

Test 5: throughput

Count: 4

Code:

  fcmp s0, s0
  setf8 w0
  setf8 w0
  setf8 w0
  setf8 w0

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5998

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
50204	24034	50104	40101	10003	40112	10004	315205	40013	50112	40209	10003	80224	20008	40001	100
50204	24004	50106	40103	10003	40112	10004	315316	40013	50112	40209	10003	80224	20008	40002	100
50204	24007	50104	40101	10003	40109	10003	314864	40012	50112	40209	10003	80224	20008	40003	100
50204	23988	50105	40102	10003	40112	10004	314891	40012	50112	40209	10003	80218	20006	40001	100
50204	23973	50109	40105	10004	40116	10004	315197	40012	50112	40209	10003	80218	20006	40002	100
50204	23968	50104	40101	10003	40112	10004	315200	40017	50116	40212	10004	80218	20006	40001	100
50204	23983	50103	40101	10002	40109	10003	315001	40017	50116	40212	10004	80224	20008	40001	100
50204	24004	50106	40103	10003	40112	10004	315003	40017	50116	40212	10004	80218	20006	40001	100
50204	23991	50104	40101	10003	40112	10004	314891	40012	50112	40209	10003	80224	20008	40002	100
50204	23987	50104	40101	10003	40112	10004	315003	40017	50116	40212	10004	80224	20008	40001	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5998

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
50024	24111	50014	40012	10002	40022	10004	316309	40000	50010	40020	10000	80020	20000	40001	10
50024	23962	50011	40011	10000	40010	10000	316249	40000	50010	40020	10000	80020	20000	40001	10
50024	23979	50011	40011	10000	40010	10000	316639	40000	50010	40020	10000	80020	20000	40001	10
50024	23993	50011	40011	10000	40010	10000	315966	40000	50010	40020	10000	80020	20000	40001	10
50024	24053	50011	40011	10000	40010	10000	316363	40000	50010	40020	10000	80020	20000	40001	10
50024	24027	50011	40011	10000	40010	10000	315455	40000	50010	40020	10000	80020	20000	40001	10
50024	23975	50011	40011	10000	40010	10000	315510	40000	50010	40020	10000	80020	20000	40001	10
50024	23993	50011	40011	10000	40010	10000	316838	40000	50010	40020	10000	80020	20000	40001	10
50024	24027	50011	40011	10000	40010	10000	316811	40000	50010	40020	10000	80020	20000	40001	10
50024	23973	50011	40011	10000	40010	10000	316209	40000	50010	40020	10000	80020	20000	40001	10

Test 6: throughput

Count: 7

Code:

  ands xzr, xzr, xzr
  setf8 w0
  setf8 w0
  setf8 w0
  setf8 w0
  setf8 w0
  setf8 w0
  setf8 w0

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5567

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	39036	80107	80107	80116	0	549553	0	0	80111	80212	0	0	140224	80013	100
80204	38961	80107	80107	80114	0	550242	0	0	80116	80216	0	0	140214	80003	100
80204	39002	80104	80104	80111	0	549803	0	0	80111	80212	0	0	140220	80003	100
80204	38984	80103	80103	80108	0	548620	0	0	80153	80253	0	0	140284	80033	100
80204	38966	80109	80109	80114	0	548982	0	0	80120	80222	0	0	140214	80004	100
80205	39044	80134	80134	80154	0	551117	0	0	80114	80216	0	0	140220	80003	100
80204	38965	80104	80104	80114	0	549756	0	0	80116	80216	0	0	140228	80007	100
80204	38967	80104	80104	80111	0	548301	0	0	80111	80212	0	0	140220	80006	100
80204	38944	80104	80104	80114	0	550424	0	0	80116	80216	0	0	140214	80003	100
80204	39022	80107	80107	80116	0	550276	0	0	80114	80216	0	0	140228	80005	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5562

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80024	39010	80030	80030	0	0	80041	0	548186	80020	80020	140020	0	0	80011	0	0	10
80024	38958	80021	80021	0	0	80020	0	550251	80020	80020	140020	0	0	80011	0	0	10
80024	38977	80021	80021	0	0	80020	0	547971	80020	80020	140020	0	0	80011	0	0	10
80024	38955	80021	80021	0	0	80020	0	549142	80020	80020	140020	0	0	80011	0	0	10
80025	38955	80061	80061	0	0	80077	0	551652	80020	80020	140020	0	0	80011	0	0	10
80024	38950	80021	80021	0	0	80020	0	550318	80020	80020	140020	0	0	80011	0	0	10
80024	38946	80021	80021	0	0	80020	0	547256	80079	80080	140020	0	0	80011	0	0	10
80024	38899	80021	80021	0	0	80020	0	548495	80020	80020	140020	0	0	80011	0	0	10
80024	38881	80021	80021	0	0	80020	0	550730	80020	80020	140020	0	0	80011	0	0	10
80024	38905	80021	80021	0	0	80020	0	550162	80020	80020	140020	0	0	80011	0	0	10

SETF8

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 2->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations