Icestorm: TST (register, lsl, 32-bit) measurements

Code:

  tst w0, w1, lsl #17

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)
1004	698	2001	2001	1000	14678	1000	1000	2000	2001
1004	698	2001	2001	1000	14678	1000	1000	2000	2001
1004	698	2001	2001	1000	14678	1000	1000	2000	2001
1004	698	2001	2001	1000	14678	1000	1000	2000	2001
1004	698	2001	2001	1000	14678	1000	1000	2000	2001
1004	698	2001	2001	1000	14678	1000	1000	2000	2001
1004	698	2001	2001	1000	14678	1000	1000	2000	2001
1004	698	2001	2001	1000	14678	1000	1000	2000	2001
1004	698	2001	2001	1000	14678	1000	1000	2000	2001
1004	698	2001	2001	1000	14678	1000	1000	2000	2001

Test 2: Latency 3->1

Chain cycles: 1

Code:

  tst w0, w1, lsl #17
  cset x0, cc

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	30030	30101	30101	20105	789247	20108	20214	30218	30001	10100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	10100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	10100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	10100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	10100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	10100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	10100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	10100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	10100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	30030	30011	30011	0	20015	789380	20010	20020	30020	30001	10010
20024	30030	30011	30011	0	20010	789438	20010	20020	30020	30001	10010
20024	30030	30011	30011	0	20010	789438	20010	20020	30020	30001	10010
20024	30030	30011	30011	0	20010	789438	20010	20020	30020	30001	10010
20024	30030	30011	30011	0	20010	789438	20010	20020	30020	30001	10010
20024	30030	30011	30011	0	20010	789438	20010	20020	30020	30001	10010
20024	30030	30011	30011	0	20010	789438	20010	20020	30020	30001	10010
20024	30030	30011	30011	0	20010	789438	20010	20020	30020	30001	10010
20024	30030	30011	30011	0	20010	789438	20010	20020	30020	30001	10010
20024	30030	30011	30011	0	20010	789438	20010	20020	30020	30001	10010

Test 3: Latency 3->2

Chain cycles: 1

Code:

  tst w0, w1, lsl #17
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	30030	30101	30101	20105	789247	20108	20214	30215	30001	10100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	10100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	10100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	10100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	10100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	10100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	10100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	10100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	10100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	30030	30011	30011	20015	789381	20015	20030	30038	30001	10010
20024	30030	30011	30011	20010	789438	20010	20020	30020	30001	10010
20024	30030	30011	30011	20010	789438	20010	20020	30020	30001	10010
20024	30030	30011	30011	20010	789438	20010	20020	30020	30001	10010
20024	30030	30011	30011	20010	789438	20010	20020	30020	30001	10010
20024	30030	30011	30011	20010	789438	20010	20020	30020	30001	10010
20024	30030	30011	30011	20010	789438	20010	20020	30020	30001	10010
20024	30030	30011	30011	20010	789438	20010	20020	30020	30001	10010
20024	30030	30011	30011	20010	789438	20010	20020	30104	30015	10010
20024	30030	30011	30011	20010	789438	20010	20020	30020	30001	10010

Test 4: throughput

Count: 8

Code:

  tst w0, w1, lsl #17
  tst w0, w1, lsl #17
  tst w0, w1, lsl #17
  tst w0, w1, lsl #17
  tst w0, w1, lsl #17
  tst w0, w1, lsl #17
  tst w0, w1, lsl #17
  tst w0, w1, lsl #17

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	53404	160117	160117	80127	1177607	80123	80224	160252	160017	100
80204	53402	160114	160114	80123	1177583	80125	80226	160248	160014	100
80204	53402	160114	160114	80123	1177619	80123	80224	160248	160014	100
80204	53402	160114	160114	80123	1177659	80123	80224	160248	160014	100
80204	53402	160114	160114	80123	1177635	80123	80224	160248	160014	100
80204	53402	160114	160114	80123	1177651	80123	80224	160248	160014	100
80204	53402	160114	160114	80123	1177627	80123	80224	160336	160065	100
80204	53402	160114	160114	80123	1177623	80123	80224	160248	160014	100
80204	53402	160114	160114	80123	1177623	80123	80224	160248	160014	100
80204	53402	160114	160114	80123	1177623	80123	80224	160248	160014	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6671

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80024	53432	160036	160036	80044	1170032	80020	80020	160020	0	160011	0	0	10
80024	53371	160021	160021	80020	1170032	80020	80020	160020	0	160011	0	0	10
80024	53371	160021	160021	80020	1170032	80020	80020	160020	0	160011	0	0	10
80024	53371	160021	160021	80020	1170032	80020	80020	160020	0	160011	0	0	10
80024	53371	160021	160021	80020	1170032	80020	80020	160020	0	160011	0	0	10
80024	53371	160021	160021	80020	1170032	80020	80020	160020	0	160011	0	0	10
80024	53371	160021	160021	80020	1170032	80020	80020	160020	0	160011	0	0	10
80024	53371	160021	160021	80020	1170032	80020	80020	160020	0	160011	0	0	10
80024	53371	160021	160021	80020	1170032	80020	80020	160020	0	160011	0	0	10
80024	53371	160021	160021	80020	1170032	80020	80020	160020	0	160011	0	0	10

TST (register, lsl, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 3->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations