Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

STR (32-bit)

Test 1: uops

Code:

  str w0, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	1149	1019	1	1018	1000	17043	1000	1000	2000	1	1000
1004	1047	1001	1	1000	1000	16883	1000	1000	2000	1	1000
1004	1039	1001	1	1000	1000	16883	1000	1000	2000	1	1000
1004	1039	1001	1	1000	1000	16883	1000	1000	2000	1	1000
1004	1039	1001	1	1000	1000	16883	1000	1000	2000	1	1000
1004	1039	1001	1	1000	1000	16883	1000	1000	2000	1	1000
1004	1039	1001	1	1000	1000	16883	1000	1000	2000	1	1000
1004	1039	1001	1	1000	1000	16883	1000	1000	2000	1	1000
1004	1039	1001	1	1000	1000	16883	1000	1000	2000	1	1000
1004	1039	1001	1	1000	1000	16883	1000	1000	2000	1	1000

Test 2: throughput

Count: 8

Code:

  str w0, [x6]
  str w0, [x6]
  str w0, [x6]
  str w0, [x6]
  str w0, [x6]
  str w0, [x6]
  str w0, [x6]
  str w0, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80206	80630	80136	101	80035	100	80001	300	1359992	80101	200	80008	200	160016	1	80000	0	100
80204	80045	80101	101	80000	100	80001	300	1359850	80101	200	80008	200	160016	1	80000	0	100
80204	80037	80101	101	80000	100	80001	300	1359850	80101	200	80008	200	160016	1	80000	0	100
80204	80037	80101	101	80000	100	80001	300	1359850	80101	200	80008	200	160016	1	80000	0	100
80204	80037	80101	101	80000	100	80001	300	1359850	80101	200	80008	200	160016	1	80000	0	100
80204	80037	80101	101	80000	100	80001	300	1359850	80101	200	80008	200	160016	1	80000	0	100
80204	80037	80101	101	80000	100	80001	300	1359850	80101	200	80008	200	160016	1	80000	0	100
80204	80037	80101	101	80000	100	80001	300	1359850	80101	200	80008	200	160016	1	80000	0	100
80204	80037	80101	101	80000	100	80001	300	1359850	80101	200	80008	200	160016	1	80000	0	100
80204	80037	80101	101	80000	100	80001	300	1359850	80101	200	80008	200	160016	1	80000	0	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	80466	80083	11	80072	10	80001	30	1360010	80011	20	80008	20	160180	1	80000	10
80024	80249	80047	11	80036	10	80036	30	1360927	80046	20	80041	20	160098	1	80000	10
80024	80040	80011	11	80000	10	80000	30	1359883	80010	20	80000	20	160000	1	80000	10
80024	80041	80011	11	80000	10	80000	30	1359883	80010	20	80000	20	160000	1	80000	10
80024	80039	80011	11	80000	10	80000	30	1359883	80010	20	80000	20	160000	1	80000	10
80024	80039	80011	11	80000	10	80000	30	1359883	80010	20	80000	20	160000	1	80000	10
80024	80039	80011	11	80000	10	80000	30	1359883	80010	20	80000	20	160000	1	80000	10
80024	80475	80083	11	80072	10	80072	30	1362259	80082	20	80082	20	160082	1	80000	10
80024	80039	80011	11	80000	10	80036	30	1360963	80046	20	80041	20	160000	1	80000	10
80024	80039	80011	11	80000	10	80000	30	1359883	80010	20	80000	20	160000	1	80000	10