Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

NEG (register, 32-bit)

Test 1: uops

Code:

  neg w0, w0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
100410301001100110002560310001000100010011000
100410301001100110002560310001000100010011000
100410301001100110002560310001000100010011000
100410301001100110002560310001000100010011000
100410301001100110002560310001000100010011000
100410301001100110002560310001000100010011000
100410301001100110002560310001000100010011000
100410301001100110002560310001000100010011000
100410301001100110002560310001000100010011000
100410301001100110002560310001000100010011000

Test 2: Latency 1->2

Code:

  neg w0, w0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204100301010110101101072593291010710214102141000110100
10204100301010110101101072595391010710212102121000110100
10204100301010110101101072595391010710212102121000110100
10204100301010110101101072595391010710212102121000110100
10204100301010110101101072595391010710212102121000110100
10204100301010110101101072595391010710212102121000110100
10204100301010110101101072595391010710212102141000110100
10204100301010110101101072595391010710212102121000110100
10204100301010110101101072595391010710212102121000110100
10204100301010110101101072595391010710212102121000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024100301002110021100282594901002810034100201001110010
10024100301002110021100202595911002010020100201001110010
10024100301002110021100202595911002010020100201001110010
10024100301002110021100202595911002010020100201001110010
10024100301002110021100202595911002010020100201001110010
10024100301002110021100202595911002010020100201001110010
10024100301002110021100202595911002010020100201001110010
10024100301002110021100202595911002010020100201001110010
10024100301002110021100202595911002010020100331001110010
10024100301002110021100202595911002010020100201001110010

Test 3: throughput

Count: 8

Code:

  neg w0, w8
  neg w1, w8
  neg w2, w8
  neg w3, w8
  neg w4, w8
  neg w5, w8
  neg w6, w8
  neg w7, w8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
80204269078011580115801200240360008012080224008022400800150080100
80204267428011580115801200240360008012080224008022400800150080100
80204267378011580115801200240360008012080224008022400800150080100
80204267378011580115801200240360008012080224008022400800150080100
80204267378011580115801200240360008012080224008022400800150080100
80204267378011580115801200240360008012080224008022400800150080100
80204267378011580115801200240360008012080224008022400800150080100
80204267378011580115801200240360008012080224008022400800150080100
80204267378011580115801200240360008012080224008022400800150080100
80204267378011580115801200240360008012080224008022400800150080100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3341

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
80024279968003780037800422774848004380046800488002980010
80024267648002180021800202774048002080020800208001180010
80024267138002180021800202774048002080020800208001180010
80024267138002180021800202774048002080020800208001180010
80024267138002180021800202774048002080020800208001180010
80024267138002180021800202774048002080020800208001180010
80024267138002180021800202774048002080020800208001180010
80024267138002180021800202774048002080020800208001180010
80024267138002180021800202774048002080020800208001180010
80024267138002180021800202774048002080020800208001180010