Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
stllrb w0, [x6]
mov x0, 0
(no loop instructions)
Retires: 1.000
Issues: 1.000
Integer unit issues: 0.001
Load/store unit issues: 1.000
SIMD/FP unit issues: 0.000
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch ldst uop (58) | simd uops in schedulers (5a) | dispatch uop (78) | map ldst uop (7d) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) |
1005 | 6159 | 1019 | 1 | 1018 | 1000 | 104730 | 1000 | 1000 | 2000 | 1 | 1000 |
1004 | 6065 | 1001 | 1 | 1000 | 1000 | 104588 | 1000 | 1000 | 2000 | 1 | 1000 |
1004 | 6058 | 1001 | 1 | 1000 | 1000 | 104588 | 1000 | 1000 | 2000 | 1 | 1000 |
1004 | 6058 | 1001 | 1 | 1000 | 1000 | 104588 | 1000 | 1000 | 2000 | 1 | 1000 |
1004 | 6058 | 1001 | 1 | 1000 | 1000 | 104588 | 1000 | 1000 | 2000 | 1 | 1000 |
1004 | 6058 | 1001 | 1 | 1000 | 1000 | 104588 | 1000 | 1000 | 2000 | 1 | 1000 |
1004 | 6058 | 1001 | 1 | 1000 | 1000 | 104588 | 1000 | 1000 | 2000 | 1 | 1000 |
1004 | 6058 | 1001 | 1 | 1000 | 1000 | 104588 | 1000 | 1000 | 2000 | 1 | 1000 |
1004 | 6058 | 1001 | 1 | 1000 | 1000 | 104588 | 1000 | 1000 | 2000 | 1 | 1000 |
1004 | 6058 | 1001 | 1 | 1000 | 1000 | 104588 | 1000 | 1000 | 2000 | 1 | 1000 |
Code:
stllrb w0, [x6] add x6, x6, 2
(fused SUBS/B.cc loop)
Result (median cycles for code): 6.0076
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
20206 | 60316 | 20212 | 10176 | 10036 | 10175 | 10000 | 35662 | 1068022 | 20101 | 10203 | 10003 | 10203 | 20006 | 10002 | 10000 | 10100 |
20204 | 60072 | 20101 | 10101 | 10000 | 10100 | 10000 | 35662 | 1067896 | 20101 | 10203 | 10003 | 10202 | 20004 | 10001 | 10000 | 10100 |
20204 | 60072 | 20101 | 10101 | 10000 | 10100 | 10000 | 35658 | 1067896 | 20100 | 10202 | 10002 | 10202 | 20004 | 10001 | 10000 | 10100 |
20204 | 60072 | 20101 | 10101 | 10000 | 10100 | 10000 | 35658 | 1067896 | 20100 | 10202 | 10002 | 10202 | 20004 | 10001 | 10000 | 10100 |
20204 | 60072 | 20101 | 10101 | 10000 | 10100 | 10000 | 35658 | 1067896 | 20100 | 10202 | 10002 | 10202 | 20004 | 10001 | 10000 | 10100 |
20204 | 60072 | 20101 | 10101 | 10000 | 10100 | 10031 | 36189 | 1069140 | 20163 | 10234 | 10034 | 10202 | 20004 | 10001 | 10000 | 10100 |
20204 | 60072 | 20101 | 10101 | 10000 | 10100 | 10000 | 35658 | 1067896 | 20100 | 10202 | 10002 | 10202 | 20004 | 10001 | 10000 | 10100 |
20204 | 60072 | 20101 | 10101 | 10000 | 10100 | 10000 | 35658 | 1067896 | 20100 | 10202 | 10002 | 10202 | 20004 | 10001 | 10000 | 10100 |
20205 | 60146 | 20151 | 10133 | 10018 | 10132 | 10000 | 35490 | 1067821 | 20101 | 10203 | 10004 | 10202 | 20004 | 10001 | 10000 | 10100 |
20204 | 60072 | 20101 | 10101 | 10000 | 10100 | 10000 | 35658 | 1067896 | 20100 | 10202 | 10002 | 10202 | 20004 | 10001 | 10000 | 10100 |
Result (median cycles for code): 6.0072
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
20026 | 60315 | 20120 | 10084 | 10036 | 10083 | 10000 | 35433 | 1068022 | 20010 | 10022 | 10002 | 10020 | 20000 | 10001 | 10000 | 10010 |
20024 | 60079 | 20011 | 10011 | 10000 | 10010 | 10000 | 35433 | 1067896 | 20010 | 10020 | 10000 | 10020 | 20000 | 10001 | 10000 | 10010 |
20024 | 60072 | 20011 | 10011 | 10000 | 10010 | 10000 | 35433 | 1067896 | 20010 | 10020 | 10000 | 10020 | 20000 | 10001 | 10000 | 10010 |
20024 | 60072 | 20011 | 10011 | 10000 | 10010 | 10000 | 35433 | 1067896 | 20010 | 10020 | 10000 | 10020 | 20000 | 10001 | 10000 | 10010 |
20024 | 60072 | 20011 | 10011 | 10000 | 10010 | 10000 | 35433 | 1067896 | 20010 | 10020 | 10000 | 10020 | 20000 | 10001 | 10000 | 10010 |
20024 | 60072 | 20011 | 10011 | 10000 | 10010 | 10000 | 35433 | 1067896 | 20010 | 10020 | 10000 | 10020 | 20000 | 10001 | 10000 | 10010 |
20024 | 60072 | 20011 | 10011 | 10000 | 10010 | 10000 | 35433 | 1067896 | 20010 | 10020 | 10000 | 10020 | 20000 | 10001 | 10000 | 10010 |
20025 | 60146 | 20061 | 10043 | 10018 | 10042 | 10000 | 35433 | 1067896 | 20010 | 10020 | 10000 | 10020 | 20000 | 10001 | 10000 | 10010 |
20024 | 60072 | 20011 | 10011 | 10000 | 10010 | 10000 | 35433 | 1067896 | 20010 | 10020 | 10000 | 10020 | 20000 | 10001 | 10000 | 10010 |
20024 | 60072 | 20011 | 10011 | 10000 | 10010 | 10000 | 35433 | 1067932 | 20010 | 10020 | 10000 | 10020 | 20000 | 10001 | 10000 | 10010 |
Code:
stllrb w0, [x6]
mov x7, 8
(fused SUBS/B.cc loop)
Result (median cycles for code): 6.0063
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
10205 | 60152 | 10119 | 101 | 10018 | 100 | 10000 | 300 | 1067730 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
10204 | 60065 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 1067730 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
10204 | 60065 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 1067730 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
10204 | 60065 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 1067730 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
10204 | 60065 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 1067730 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
10204 | 60065 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 1067730 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
10204 | 60065 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 1067730 | 10100 | 200 | 10004 | 200 | 20104 | 1 | 10000 | 100 |
10204 | 60065 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 1067730 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
10204 | 60065 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 1067730 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
10204 | 60065 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 1067730 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
Result (median cycles for code): 6.0063
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
10024 | 60065 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 1067730 | 10010 | 20 | 10004 | 20 | 20008 | 1 | 10000 | 10 |
10024 | 60063 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 1067694 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |
10024 | 60063 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 1067694 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |
10024 | 60064 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 1067694 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |
10024 | 60063 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 1067694 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |
10024 | 60063 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 1067694 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |
10024 | 60063 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 1067694 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |
10024 | 60063 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 1067694 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |
10024 | 60063 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 1067694 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |
10024 | 60063 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 1067694 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |