Icestorm: LDRSH (unsigned offset, 64-bit) measurements

Code:

  ldrsh x0, [x6, #8]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	682	1025	1	1024	1000	8238	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8112	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8130	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8148	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8310	1000	1000	1000	1	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh x0, [x6, #8]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70153	40108	30107	10001	30130	10003	1859485	693973	40106	30212	10004	60224	10004	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	10004	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	10004	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	10004	30003	10000	30100
40205	70077	40111	30109	10002	30135	10003	1859581	694063	40106	30212	10004	60224	10004	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	10004	30003	10000	30100
40204	70115	40103	30103	10000	30103	10003	1859905	694195	40106	30212	10004	60224	10004	30003	10000	30100
40204	70052	40103	30103	10000	30103	10015	1859953	694191	40150	30251	10017	60224	10004	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	10004	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	10004	30003	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
40025	70152	40018	30017	10001	30040	10003	1859677	694713	40016	30032	10004	60020	10000	30003	10000	0	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	10000	30003	10000	0	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	10000	30003	10000	0	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	10000	30003	10000	0	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	10000	30003	10000	0	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	10000	30003	10000	0	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	10000	30003	10000	0	30010
40024	70049	40013	30013	10000	30010	10015	1860070	694875	40060	30071	10017	60020	10000	30003	10000	0	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	10000	30003	10000	0	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	10000	30003	10000	0	30010

Test 3: throughput

Count: 8

Code:

  ldrsh x0, [x6, #8]
  ldrsh x0, [x6, #8]
  ldrsh x0, [x6, #8]
  ldrsh x0, [x6, #8]
  ldrsh x0, [x6, #8]
  ldrsh x0, [x6, #8]
  ldrsh x0, [x6, #8]
  ldrsh x0, [x6, #8]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40181	80129	101	80028	100	80008	300	256190	80108	200	80012	200	80072	1	80000	100
80204	40085	80101	101	80000	100	80008	300	640160	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640070	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640070	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640070	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640070	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640124	80108	200	80012	200	80014	1	80000	100
80204	40055	80105	101	80004	100	80008	300	280136	80108	200	80012	200	80012	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	80012	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640178	80108	200	80012	200	80012	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40253	80041	11	80030	10	80008	30	320190	80018	20	80012	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	80010	20	80000	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	80010	20	80000	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	80010	20	80000	20	80069	1	80000	10
80024	40059	80011	11	80000	10	80000	30	640166	80010	20	80000	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	80010	20	80000	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	80010	20	80000	20	80000	1	80000	10
80024	40164	80011	11	80000	10	80000	30	640364	80010	20	80000	20	80000	1	80000	10
80024	40055	80011	11	80000	10	80000	30	640310	80010	20	80000	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	80010	20	80000	20	80000	1	80000	10

LDRSH (unsigned offset, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations