Icestorm: LDR (register, sxtw, 32-bit) measurements

Code:

  ldr w0, [x6, w7, sxtw]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	1158	1031	1	1030	1000	8166	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8040	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	2000	1	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldr w0, [x6, w7, sxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70154	40108	30107	10001	30130	10003	1859533	693921	40106	30210	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859533	693921	40106	30210	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40205	70077	40111	30109	10002	30135	10003	1860013	694239	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70122	40103	30103	10000	30103	10003	1859851	694173	40106	30212	10004	60528	20112	30040	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70290	40018	30017	10001	30040	10003	1859893	693806	40016	30030	10004	60020	20000	30003	10000	30010
40024	70051	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859733	694744	40010	30020	10000	60020	20000	30003	10000	30010
40024	70048	40013	30013	10000	30010	10000	1859679	694725	40010	30020	10000	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60116	20034	30009	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	20000	30003	10000	30010

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldr w0, [x6, w7, sxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70156	40108	30107	10001	30130	10003	1859566	693909	40106	30210	10004	60220	20008	30004	10000	30100
40204	70104	40104	30104	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40206	70189	40122	30118	10004	30169	10003	1859776	694018	40106	30210	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10015	1860736	694510	40150	30251	10017	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	20008	30003	10000	30100
40204	70047	40103	30103	10000	30103	10015	1859926	694180	40150	30251	10017	60224	20008	30004	10000	30100
40204	70072	40104	30104	10000	30103	10003	1859539	693896	40106	30210	10004	60224	20008	30003	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70160	40018	30017	10001	30040	10003	1859623	693696	40016	30030	10004	60020	20000	30003	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10015	1859827	694067	40060	30067	10017	60020	20000	30002	10000	30010
40024	70044	40012	30012	10000	30010	10015	1860718	694359	40060	30067	10017	60020	20000	30002	10000	30010
40024	70041	40012	30012	10000	30010	10000	1859571	694684	40010	30020	10000	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	20000	30002	10000	30010

Test 4: throughput

Count: 8

Code:

  ldr w0, [x6, w7, sxtw]
  ldr w0, [x6, w7, sxtw]
  ldr w0, [x6, w7, sxtw]
  ldr w0, [x6, w7, sxtw]
  ldr w0, [x6, w7, sxtw]
  ldr w0, [x6, w7, sxtw]
  ldr w0, [x6, w7, sxtw]
  ldr w0, [x6, w7, sxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40158	80129	101	80028	100	80008	300	248136	80108	200	80012	200	160028	1	80000	100
80204	40050	80101	101	80000	100	80008	300	640142	80108	200	80012	200	160024	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	160024	1	80000	100
80204	40049	80101	101	80000	100	80056	300	413886	80156	200	80069	200	160024	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	160024	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	160024	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	160024	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	160024	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	160024	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	160024	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5009

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40321	80043	11	80032	10	80000	30	320238	80010	20	80000	20	160000	1	80000	10
80025	40110	80042	11	80031	10	80000	30	352320	80010	20	80000	20	160000	1	80000	10
80024	40075	80011	11	80000	10	80000	30	640616	80010	20	80000	20	160000	1	80000	10
80024	40075	80011	11	80000	10	80000	30	640616	80010	20	80000	20	160000	1	80000	10
80024	40075	80011	11	80000	10	80000	30	640616	80010	20	80000	20	160000	1	80000	10
80024	40075	80011	11	80000	10	80000	30	640616	80010	20	80000	20	160000	1	80000	10
80024	40075	80011	11	80000	10	80000	30	640616	80010	20	80000	20	160000	1	80000	10
80024	40075	80011	11	80000	10	80000	30	640616	80010	20	80000	20	160000	1	80000	10
80024	40075	80011	11	80000	10	80000	30	640616	80010	20	80000	20	160000	1	80000	10
80024	40075	80011	11	80000	10	80000	30	640616	80010	20	80000	20	160000	1	80000	10

LDR (register, sxtw, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations