Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SUBS (sxth, 64-bit)

Test 1: uops

Code:

  subs x0, x0, w1, sxth
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000

Test 2: Latency 1->2

Code:

  subs x0, x0, w1, sxth
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
10204200302010120101101045290441010410206202160200010010100
10204200302010120101101045290871010410208202160200010010100
10204200302010120101101045290441010410206202160200010010100
10204200302010120101101045290871010410208202160200010010100
10204200302010120101101045290871010410208202160200010010100
10204200302010120101101045290871010410208202160200010010100
10204200302010120101101045290871010410208202160200010010100
10204200302010120101101045290871010410208202160200010010100
10204200302010120101101045290871010410208202160200010010100
10204200302010120101101045290871010410208202160200010010100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10025200602003520035100580529216010025100320200202001110010
10024200302002120021100200529249010020100200200202001110010
10024200302002120021100200529249010020100200200202001110010
10024200302002120021100200529249010020100200200202001110010
10024200302002120021100200529249010020100200200202001110010
10024200302002120021100200529249010020100200200202001110010
10024200302002120021100200529249010020100200200202001110010
10024200302002120021100200529249010020100200200202001110010
10024200302002120021100200529249010020100200200202001110010
10024200302002120021100200529249010020100200200202001110010

Test 3: Latency 1->3

Code:

  subs x0, x1, w0, sxth
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204200302010120101101045290011010410206202122000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024200302002120021100255292151002510030200202001110010
10024200302002120021100205292491002010020200982003210010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10025200602003520035100585292491002010020200942003210010
10024200302002120021100205292491002010020200202001110010
10025200602003520035100585292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010

Test 4: Latency 4->2

Chain cycles: 1

Code:

  subs x0, x1, w2, sxth
  cset x1, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
2020430030301013010120106078948800201432025700302153000120100
2020430030301013010120105078936900201052021200302183000120100
2020430030301013010120105078936900201052021200302183000120100
2020430030301013010120105078936900201052021200302183000120100
2020430030301013010120105078936900201052021200302183000120100
2020430030301013010120105078936900201052021200302183000120100
2020430030301013010120105078936900201052021200302183000120100
2020430030301013010120105078936900201052021200302183000120100
2020430030301013010120105078936900201052021200302183000120100
2020430030301013010120105078936900201052021200302183000120100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20024300303001130011200157893082001520032300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010

Test 5: Latency 4->3

Chain cycles: 1

Code:

  subs x0, x1, w2, sxth
  cset x2, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20204300303010130101201067891512010520212302153000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20024300303001130011200157894592001520032300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107897922005020074300203000120010
20025300603002530025200507893802001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010

Test 6: throughput

Count: 8

Code:

  subs x0, x8, w9, sxth
  subs x1, x8, w9, sxth
  subs x2, x8, w9, sxth
  subs x3, x8, w9, sxth
  subs x4, x8, w9, sxth
  subs x5, x8, w9, sxth
  subs x6, x8, w9, sxth
  subs x7, x8, w9, sxth
  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
80204534301601181601180801241099575801238022416024816001480100
80204534041601141601140801231100360801648026416025616002280100
80204534041601141601140801231100076801238022416024816001480100
80204534041601141601140801231100076801238022416024816001480100
80204534041601141601140801231100076801238022416024816001480100
80204534041601141601140801231100076801238022416024816001480100
80204534041601141601140801231100076801238022416024816001480100
80204534041601141601140801231100076801238022416024816001480100
80204534041601141601140801231100076801238022416024816001480100
80204534041601141601140801231100076801238022416024816001480100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6671

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
8002553424160084160084800841107842800488004816007616003280010
8002453371160021160021800201107732800208002016002016001180010
8002453371160021160021800201107732800208002016002016001180010
8002453371160021160021800201107732800208002016002016001180010
8002453371160021160021800201107751800838008416002016001180010
8002453371160021160021800201107732800208002016002016001180010
8002453371160021160021800201107732800208002016002016001180010
8002453371160021160021800201107732800208002016002016001180010
8002453371160021160021800201107732800208002016002016001180010
8002453371160021160021800201107732800208002016002016001180010