Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

PRFM (register, PLDL3KEEP)

Test 1: uops

Code:

  prfm pldl3keep, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1004	2470	1001	1	1000	1000	34906	1000	1000	1000	1	1000
1004	2097	1001	1	1000	1000	34906	1000	1000	1000	1	1000
1004	2097	1001	1	1000	1000	34906	1000	1000	1000	1	1000
1004	2097	1001	1	1000	1000	34906	1000	1000	1000	1	1000
1004	2097	1001	1	1000	1000	34906	1000	1000	1000	1	1000
1004	2097	1001	1	1000	1000	34906	1000	1000	1000	1	1000
1004	2101	1001	1	1000	1000	34906	1000	1000	1000	1	1000
1004	2097	1001	1	1000	1000	34918	1000	1000	1000	1	1000
1004	2101	1001	1	1000	1000	34804	1000	1000	1000	1	1000
1004	2075	1001	1	1000	1000	34586	1000	1000	1000	1	1000

Test 2: throughput

Code:

  prfm pldl3keep, [x6]
  add x6, x6, 64

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20204	21208	20102	10102	10000	10101	10002	61288	349629	20109	10209	10009	10207	10007	10006	10000	10100
20204	20894	20347	10227	10120	10230	10002	61239	349997	20110	10210	10010	10211	10011	10007	10000	10100
20204	20107	20105	10105	10000	10110	10004	61417	348737	20114	10212	10012	10208	10008	10002	10000	10100
20204	20117	20101	10101	10000	10100	10000	61161	350463	20102	10204	10004	10206	10006	10002	10000	10100
20204	20092	20103	10103	10000	10108	10000	61292	349761	20102	10204	10004	10202	10002	10001	10000	10100
20204	20015	20103	10103	10000	10102	10000	61318	351219	20106	10208	10008	10202	10002	10001	10000	10100
20204	20146	20103	10103	10000	10104	10000	61079	349039	20102	10204	10004	10202	10002	10001	10000	10100
20204	20036	20103	10103	10000	10105	10000	61646	347079	20105	10207	10007	10208	10008	10005	10000	10100
20204	20064	20102	10102	10000	10106	10000	61687	346695	20102	10204	10004	10202	10002	10001	10000	10100
20204	19972	20102	10102	10000	10106	10000	61593	347725	20106	10208	10008	10206	10006	10002	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0065

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20024	21018	20011	10011	10000	10013	10000	61384	347907	20012	10024	10004	10022	10002	10001	10000	10010
20024	20035	20011	10011	10000	10010	10000	60910	348667	20010	10020	10000	10020	10000	10001	10000	10010
20024	19974	20011	10011	10000	10010	10000	60562	348461	20010	10020	10000	10020	10000	10001	10000	10010
20024	19840	20011	10011	10000	10010	10000	61026	349113	20010	10020	10000	10020	10000	10001	10000	10010
20024	19966	20011	10011	10000	10010	10000	60739	348091	20010	10020	10000	10020	10000	10001	10000	10010
20024	19990	20011	10011	10000	10010	10000	60980	347403	20010	10020	10000	10020	10000	10001	10000	10010
20024	19808	20011	10011	10000	10010	10000	61267	346363	20010	10020	10000	10020	10000	10001	10000	10010
20024	19964	20011	10011	10000	10010	10000	60875	347907	20010	10020	10000	10020	10000	10001	10000	10010
20024	20090	20011	10011	10000	10010	10000	61017	347727	20010	10020	10000	10020	10000	10001	10000	10010
20024	19896	20011	10011	10000	10010	10000	60864	347979	20010	10020	10000	10020	10000	10001	10000	10010

Test 3: throughput

Code:

  prfm pldl3keep, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0058

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10204	20058	10101	101	10000	100	10000	300	350066	10100	200	10006	200	10004	1	10000	100
10204	20058	10101	101	10000	100	10006	300	349086	10106	200	10012	200	10012	1	10000	100
10204	20058	10101	101	10000	100	10006	300	349160	10106	200	10012	200	10012	1	10000	100
10204	20058	10101	101	10000	100	10006	300	349160	10106	200	10012	200	10012	1	10000	100
10204	20058	10101	101	10000	100	10006	300	349160	10106	200	10012	200	10012	1	10000	100
10204	20058	10101	101	10000	100	10006	300	349160	10106	200	10012	200	10012	1	10000	100
10204	20058	10101	101	10000	100	10006	300	349160	10106	200	10012	200	10012	1	10000	100
10204	20058	10101	101	10000	100	10006	300	349160	10106	200	10012	200	10012	1	10000	100
10204	20058	10101	101	10000	100	10006	300	349160	10106	200	10012	200	10012	1	10000	100
10204	20058	10101	101	10000	100	10006	300	349160	10106	200	10012	200	10012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0058

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10024	20055	10011	11	10000	10	10000	30	349136	10010	20	10000	20	10000	1	10000	10
10024	20058	10011	11	10000	10	10000	30	349136	10010	20	10000	20	10000	1	10000	10
10024	20058	10011	11	10000	10	10000	30	349136	10010	20	10000	20	10000	1	10000	10
10024	20058	10011	11	10000	10	10000	30	349136	10010	20	10000	20	10000	1	10000	10
10024	20058	10011	11	10000	10	10000	30	349136	10010	20	10000	20	10000	1	10000	10
10024	20058	10011	11	10000	10	10000	30	349136	10010	20	10000	20	10000	1	10000	10
10024	20058	10011	11	10000	10	10000	30	349136	10010	20	10000	20	10000	1	10000	10
10024	20058	10011	11	10000	10	10000	30	349136	10010	20	10000	20	10000	1	10000	10
10024	20058	10011	11	10000	10	10000	30	349136	10010	20	10000	20	10000	1	10000	10
10024	20058	10011	11	10000	10	10000	30	349136	10010	20	10000	20	10000	1	10000	10