Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

STLXP (64-bit)

Test 1: uops

Code:

  stlxp w0, x1, x2, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	3159	1019	1	1018	1000	51855	1000	1000	3000	1	1000
1004	3047	1001	1	1000	1000	51855	1000	1000	3000	1	1000
1004	3047	1001	1	1000	1000	51855	1000	1000	3000	1	1000
1004	3047	1001	1	1000	1000	51855	1000	1000	3000	1	1000
1004	3047	1001	1	1000	1000	51855	1000	1000	3000	1	1000
1004	3047	1001	1	1000	1000	51855	1000	1000	3000	1	1000
1004	3047	1001	1	1000	1000	51855	1000	1000	3000	1	1000
1004	3047	1001	1	1000	1000	51855	1000	1000	3000	1	1000
1005	3087	1019	1	1018	1000	51855	1000	1000	3000	1	1000
1004	3047	1001	1	1000	1000	51855	1000	1000	3000	1	1000

Test 2: throughput

Code:

  stlxp w0, x1, x2, [x6]
  add x6, x6, 16

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.2364

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20214	33996	20533	10353	10180	10352	10003	35477	365260	20106	10203	10003	10203	30009	10004	10000	10100
20204	32379	20104	10104	10000	10103	10002	35491	364327	20104	10202	10002	10202	30006	10003	10000	10100
20204	32377	20103	10103	10000	10102	10002	35491	364164	20104	10202	10002	10202	30006	10003	10000	10100
20204	32455	20103	10103	10000	10102	10002	35491	364146	20104	10202	10002	10202	30006	10003	10000	10100
20204	32375	20103	10103	10000	10102	10002	35491	364331	20104	10202	10002	10202	30006	10003	10000	10100
20204	32372	20103	10103	10000	10102	10002	35491	364336	20104	10202	10002	10202	30006	10003	10000	10100
20204	32378	20103	10103	10000	10102	10002	35491	364072	20104	10202	10002	10202	30006	10003	10000	10100
20204	32389	20103	10103	10000	10102	10002	35491	364261	20104	10202	10002	10202	30006	10003	10000	10100
20204	32377	20103	10103	10000	10102	10002	35491	364040	20104	10202	10002	10202	30006	10003	10000	10100
20204	32381	20103	10103	10000	10102	10002	35491	364127	20104	10202	10002	10202	30006	10003	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.2572

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20034	36351	20448	10268	10180	10267	10002	35242	367209	20014	10022	10002	10020	30000	10001	10000	10010
20024	32604	20011	10011	10000	10010	10000	35259	366798	20010	10020	10000	10020	30000	10001	10000	10010
20025	32643	20062	10044	10018	10043	10000	35242	366605	20010	10020	10000	10020	30000	10001	10000	10010
20024	32570	20011	10011	10000	10010	10000	35259	366835	20010	10020	10000	10020	30000	10001	10000	10010
20024	32578	20011	10011	10000	10010	10000	35259	366640	20010	10020	10000	10020	30000	10001	10000	10010
20024	32577	20011	10011	10000	10010	10000	35259	366797	20010	10020	10000	10020	30000	10001	10000	10010
20024	32582	20011	10011	10000	10010	10000	35259	366636	20010	10020	10000	10020	30000	10001	10000	10010
20024	32575	20011	10011	10000	10010	10000	35259	366788	20010	10020	10000	10020	30000	10001	10000	10010
20024	32578	20011	10011	10000	10010	10000	35259	366762	20010	10020	10000	10020	30000	10001	10000	10010
20024	32577	20011	10011	10000	10010	10000	35259	366744	20010	10020	10000	10020	30000	10001	10000	10010

Test 3: throughput

Code:

  stlxp w0, x1, x2, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10205	30518	10119	101	10018	100	10000	300	528855	10100	200	10004	200	30012	1	10000	100
10204	30047	10101	101	10000	100	10000	300	528855	10100	200	10004	200	30012	1	10000	100
10204	30040	10101	101	10000	100	10000	300	528855	10100	200	10004	200	30012	1	10000	100
10204	30040	10101	101	10000	100	10000	300	528855	10100	200	10004	200	30012	1	10000	100
10204	30040	10101	101	10000	100	10000	300	528855	10100	200	10004	200	30012	1	10000	100
10204	30040	10101	101	10000	100	10000	300	530236	10100	200	10006	200	30012	1	10000	100
10204	30048	10101	101	10000	100	10000	300	529017	10100	200	10004	200	30012	1	10000	100
10204	30044	10101	101	10000	100	10000	300	528945	10100	200	10004	200	30012	1	10000	100
10204	30040	10101	101	10000	100	10000	300	528855	10100	200	10004	200	30012	1	10000	100
10204	30046	10101	101	10000	100	10000	300	528855	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10025	30162	10029	11	10018	10	10000	30	528855	10010	20	10004	20	30000	1	10000	10
10024	30047	10011	11	10000	10	10000	30	528855	10010	20	10000	20	30000	1	10000	10
10025	30087	10029	11	10018	10	10000	30	528855	10010	20	10000	20	30000	1	10000	10
10024	30047	10011	11	10000	10	10000	30	528855	10010	20	10000	20	30000	1	10000	10
10024	30047	10011	11	10000	10	10000	30	528855	10010	20	10000	20	30000	1	10000	10
10024	30102	10011	11	10000	10	10000	30	528855	10010	20	10000	20	30000	1	10000	10
10024	30055	10011	11	10000	10	10000	30	528855	10010	20	10000	20	30000	1	10000	10
10024	30047	10011	11	10000	10	10000	30	528855	10010	20	10000	20	30000	1	10000	10
10024	30047	10011	11	10000	10	10000	30	528855	10010	20	10000	20	30000	1	10000	10
10024	30047	10011	11	10000	10	10000	30	528855	10010	20	10000	20	30000	1	10000	10