Icestorm: STP (post-index, 64-bit) measurements

Code:

  stp x0, x1, [x6], #8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	1507	2059	1041	1018	1040	1000	4657	19081	2000	1000	3000	1001	1000
1004	1135	2001	1001	1000	1000	1000	4657	19081	2000	1000	3000	1001	1000
1004	1156	2001	1001	1000	1000	1000	4657	18116	2000	1000	3000	1001	1000
1004	1151	2001	1001	1000	1000	1000	4661	18451	2000	1000	3000	1001	1000
1004	1156	2001	1001	1000	1000	1000	4661	18937	2000	1000	3000	1001	1000
1004	1158	2001	1001	1000	1000	1000	4657	19063	2000	1000	3000	1001	1000
1004	1154	2001	1001	1000	1000	1000	4657	18055	2000	1000	3000	1001	1000
1004	1155	2001	1001	1000	1000	1000	4657	19027	2000	1000	3000	1001	1000
1004	1158	2001	1001	1000	1000	1000	4657	19009	2000	1000	3000	1001	1000
1004	1181	2001	1001	1000	1000	1000	4657	19063	2000	1000	3000	1001	1000

Test 2: Latency 3->3

Code:

  stp x0, x1, [x6], #8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0600

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10209	11871	20404	10314	10090	10314	10003	44673	180469	20109	200	10010	200	30030	10005	10000	100
10204	10601	20104	10104	10000	10104	10002	43518	180641	20106	200	10008	200	30024	10004	10000	100
10204	10644	20104	10104	10000	10104	10002	43516	181307	20106	200	10008	200	30024	10004	10000	100
10204	10645	20104	10104	10000	10104	10002	43518	180641	20106	200	10008	200	30024	10004	10000	100
10204	10619	20104	10104	10000	10104	10002	43518	180767	20106	200	10008	200	30024	10004	10000	100
10204	10639	20104	10104	10000	10104	10002	43517	180803	20106	200	10008	200	30024	10004	10000	100
10204	10619	20104	10104	10000	10104	10002	43517	180335	20106	200	10008	200	30024	10004	10000	100
10204	10650	20104	10104	10000	10104	10002	43519	180713	20106	200	10008	200	30024	10004	10000	100
10204	10647	20104	10104	10000	10104	10002	43518	180965	20106	200	10008	200	30024	10004	10000	100
10204	10630	20104	10104	10000	10104	10002	43517	180821	20106	200	10008	200	30024	10004	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0647

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10029	11855	20307	10217	10090	10218	10002	42985	180857	20016	20	10008	20	30000	10001	10000	10
10024	10635	20011	10011	10000	10010	10000	42969	180923	20010	20	10000	20	30000	10001	10000	10
10024	10642	20011	10011	10000	10010	10000	42973	181013	20010	20	10000	20	30000	10001	10000	10
10024	10635	20011	10011	10000	10010	10000	42966	180941	20010	20	10000	20	30000	10001	10000	10
10024	10654	20011	10011	10000	10010	10000	42968	180635	20010	20	10000	20	30000	10001	10000	10
10024	10675	20011	10011	10000	10010	10000	42978	181247	20010	20	10000	20	30000	10001	10000	10
10024	10659	20011	10011	10000	10010	10000	42978	180401	20010	20	10000	20	30000	10001	10000	10
10024	10623	20011	10011	10000	10010	10000	42977	181103	20010	20	10000	20	30000	10001	10000	10
10024	10663	20011	10011	10000	10010	10000	42982	180721	20010	20	10000	20	30030	10005	10000	10
10024	10661	20014	10014	10000	10014	10000	42933	180941	20010	20	10000	20	30000	10001	10000	10

Test 3: throughput

Count: 8

Code:

  stp x0, x1, [x6], #8
  stp x0, x1, [x7], #8
  stp x0, x1, [x8], #8
  stp x0, x1, [x9], #8
  stp x0, x1, [x10], #8
  stp x0, x1, [x11], #8
  stp x0, x1, [x12], #8
  stp x0, x1, [x13], #8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0139

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80209	81964	160401	80311	80090	80311	80003	240318	1378616	160109	200	80010	200	240024	80005	80000	100
80204	81085	160105	80105	80000	80104	80002	240312	1378704	160106	200	80008	200	240024	80005	80000	100
80204	81073	160105	80105	80000	80104	80002	240312	1378501	160106	200	80008	200	240144	80037	80000	100
80204	81076	160105	80105	80000	80104	80002	240312	1378501	160106	200	80008	200	240024	80005	80000	100
80204	81076	160105	80105	80000	80104	80035	240419	1379120	160175	200	80048	200	240024	80005	80000	100
80204	81073	160105	80105	80000	80104	80002	240312	1378501	160106	200	80008	200	240024	80005	80000	100
80204	81073	160105	80105	80000	80104	80002	240312	1378501	160106	200	80008	200	240024	80005	80000	100
80204	81073	160105	80105	80000	80104	80002	240312	1378501	160106	200	80008	200	240024	80005	80000	100
80204	81073	160105	80105	80000	80104	80035	240419	1379133	160175	200	80048	200	240024	80005	80000	100
80204	81145	160105	80105	80000	80104	80002	240312	1379208	160106	200	80008	200	240024	80005	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0139

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80029	82037	160305	80215	80090	80214	80002	240042	1378661	160016	20	80008	20	240000	80001	80000	10
80024	81073	160011	80011	80000	80010	80000	240030	1378495	160010	20	80000	20	240000	80001	80000	10
80024	81073	160011	80011	80000	80010	80000	240030	1378495	160010	20	80000	20	240000	80001	80000	10
80024	81073	160011	80011	80000	80010	80000	240030	1378495	160010	20	80000	20	240000	80001	80000	10
80024	81073	160011	80011	80000	80010	80000	240030	1378495	160010	20	80000	20	240000	80001	80000	10
80024	81073	160011	80011	80000	80010	80035	240149	1379151	160085	20	80048	20	240000	80001	80000	10
80024	81073	160011	80011	80000	80010	80000	240030	1378495	160010	20	80000	20	240000	80001	80000	10
80024	81073	160011	80011	80000	80010	80000	240030	1378495	160010	20	80000	20	240000	80001	80000	10
80024	81073	160011	80011	80000	80010	80000	240030	1378495	160010	20	80000	20	240000	80001	80000	10
80024	81073	160011	80011	80000	80010	80000	240030	1378495	160010	20	80000	20	240000	80001	80000	10

STP (post-index, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations