Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

MRS (FPSR)

Test 1: uops

Code:

  mrs x0, fpsr

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	? int output thing (e9)	? int retires (ef)
1004	7024	1001	1001	1001	1000
1004	7024	1001	1001	1001	1000
1004	7024	1001	1001	1001	1000
1004	7024	1001	1001	1001	1000
1004	7024	1001	1001	1001	1000
1004	7024	1001	1001	1001	1000
1004	7024	1001	1001	1001	1000
1004	7024	1001	1001	1001	1000
1004	7024	1001	1001	1001	1000
1004	7024	1001	1001	1001	1000

Test 2: throughput

Count: 8

Code:

  mrs x0, fpsr
  mrs x1, fpsr
  mrs x2, fpsr
  mrs x3, fpsr
  mrs x4, fpsr
  mrs x5, fpsr
  mrs x6, fpsr
  mrs x7, fpsr

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 7.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	560034	80101	80101	100	300	100	200	200	80001	80100
80206	560076	80101	80101	100	300	100	200	200	80001	80100
80205	560052	80101	80101	100	300	100	200	200	80001	80100
80205	560052	80101	80101	100	300	100	200	200	80001	80100
80204	560028	80101	80101	100	300	100	200	200	80001	80100
80204	560028	80101	80101	100	300	100	200	200	80001	80100
80204	560028	80101	80101	100	300	100	200	200	80001	80100
80204	560028	80101	80101	100	300	100	200	200	80001	80100
80204	560028	80101	80101	100	300	100	200	200	80001	80100
80204	560028	80101	80101	100	300	100	200	200	80001	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 7.0003

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	560029	80011	80011	0	10	30	10	20	20	80001	80010
80024	560024	80011	80011	0	10	30	10	20	20	80001	80010
80024	560024	80011	80011	0	10	30	10	20	20	80001	80010
80024	560024	80011	80011	0	10	30	10	20	20	80001	80010
80025	560055	80011	80011	0	10	30	10	20	20	80001	80010
80025	560052	80011	80011	0	10	30	10	20	20	80001	80010
80024	560024	80011	80011	0	10	30	10	20	20	80001	80010
80024	560024	80011	80011	0	10	30	10	20	20	80001	80010
80024	560024	80011	80011	0	10	30	10	20	20	80001	80010
80024	560024	80011	80011	0	10	30	10	20	20	80001	80010