Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMN (immediate, 64-bit)

Test 1: uops

Code:

  cmn x0, #3

Initialization

  mov x0, 1

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)
1004	534	1001	1001	1000	3000	1000	1000	1000	1001
1004	398	1001	1001	1000	3000	1000	1000	1000	1001
1004	395	1001	1001	1000	3000	1000	1000	1000	1001
1004	395	1001	1001	1000	3000	1000	1000	1000	1001
1004	391	1001	1001	1000	3000	1000	1000	1000	1001
1004	390	1001	1001	1000	3000	1000	1000	1000	1001
1004	392	1001	1001	1000	3000	1000	1000	1000	1001
1004	389	1001	1001	1000	3000	1000	1000	1000	1001
1004	392	1001	1001	1000	3000	1000	1000	1000	1001
1004	389	1001	1001	1000	3000	1000	1000	1000	1001

Test 2: Latency 2->1

Chain cycles: 1

Code:

  cmn x0, #3
  cset x0, cc

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20108	519312	20107	20212	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519495	20018	20036	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20036	20001	10010
20024	20030	20011	20011	20018	519476	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010

Test 3: throughput

Count: 8

Code:

  cmn x0, #3
  cmn x0, #3
  cmn x0, #3
  cmn x0, #3
  cmn x0, #3
  cmn x0, #3
  cmn x0, #3
  cmn x0, #3

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3635

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	29287	80113	80113	80118	240354	80118	80220	80216	80012	100
80204	29157	80114	80114	80118	240354	80118	80220	80220	80013	100
80204	29166	80113	80113	80118	240360	80120	80220	80220	80013	100
80204	29052	80113	80113	80118	240354	80118	80220	80220	80012	100
80204	29166	80113	80113	80118	240354	80118	80220	80220	80013	100
80204	29077	80113	80113	80118	240354	80118	80220	80220	80013	100
80204	29168	80115	80115	80120	240354	80118	80220	80220	80013	100
80204	29068	80113	80113	80118	240354	80118	80220	80220	80013	100
80204	29166	80113	80113	80118	240354	80118	80220	80220	80013	100
80204	29072	80112	80112	80117	240474	80158	80260	80220	80013	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3631

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	30077	80035	80035	80039	240143	80039	80042	80020	80011	10
80024	29168	80021	80021	80020	240099	80020	80020	80020	80011	10
80024	29086	80021	80021	80020	240068	80020	80020	80020	80011	10
80024	29130	80021	80021	80020	240063	80020	80020	80040	80024	10
80024	29113	80060	80060	80059	240075	80020	80020	80020	80011	10
80024	29132	80021	80021	80020	240190	80058	80058	80020	80011	10
80024	29045	80021	80021	80020	240082	80020	80020	80020	80011	10
80024	28992	80021	80021	80020	240307	80099	80099	80020	80011	10
80024	28941	80021	80021	80020	240299	80095	80095	80020	80011	10
80024	29119	80021	80021	80020	240066	80020	80020	80020	80011	10