Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
swpal x0, x1, [x6] nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0
(no loop instructions)
Retires (minus 70 nops): 2.000
Issues: 2.000
Integer unit issues: 0.001
Load/store unit issues: 2.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch ldst uop (58) | simd uops in schedulers (5a) | dispatch uop (78) | map ldst uop (7d) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) |
| 72005 | 37745 | 2005 | 1 | 2004 | 2002 | 11802 | 2002 | 2002 | 4000 | 1 | 2000 |
| 72004 | 34378 | 2001 | 1 | 2000 | 2000 | 11772 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34457 | 2001 | 1 | 2000 | 2000 | 11772 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34266 | 2001 | 1 | 2000 | 2000 | 11772 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34613 | 2001 | 1 | 2000 | 2000 | 11772 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34148 | 2001 | 1 | 2000 | 2000 | 11772 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34153 | 2001 | 1 | 2000 | 2000 | 11772 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34168 | 2001 | 1 | 2000 | 2000 | 11772 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34146 | 2001 | 1 | 2000 | 2000 | 11772 | 2000 | 2000 | 4004 | 1 | 2000 |
| 72004 | 34308 | 2001 | 1 | 2000 | 2000 | 11772 | 2000 | 2000 | 4000 | 1 | 2000 |
Code:
swpal x0, x1, [x6] add x6, x6, 8
(fused SUBS/B.cc loop)
Result (median cycles for code): 6.0061
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) |
| 30209 | 60700 | 30222 | 10139 | 20083 | 10140 | 20004 | 35252 | 126821 | 30106 | 10202 | 20004 | 10202 | 40008 | 0 | 10001 | 20000 | 0 | 10100 |
| 30204 | 60061 | 30101 | 10101 | 20000 | 10101 | 20002 | 35249 | 126953 | 30103 | 10201 | 20003 | 10201 | 40005 | 0 | 10001 | 20000 | 0 | 10100 |
| 30204 | 60061 | 30103 | 10101 | 20002 | 10102 | 20002 | 35249 | 126938 | 30103 | 10201 | 20003 | 10201 | 40005 | 0 | 10001 | 20000 | 0 | 10100 |
| 30204 | 60061 | 30101 | 10101 | 20000 | 10101 | 20002 | 35249 | 126922 | 30103 | 10201 | 20003 | 10201 | 40005 | 0 | 10001 | 20000 | 0 | 10100 |
| 30204 | 60061 | 30101 | 10101 | 20000 | 10101 | 20002 | 35249 | 126944 | 30103 | 10201 | 20003 | 10201 | 40005 | 0 | 10001 | 20000 | 0 | 10100 |
| 30204 | 60061 | 30101 | 10101 | 20000 | 10101 | 20002 | 35249 | 126829 | 30103 | 10201 | 20003 | 10201 | 40005 | 0 | 10001 | 20000 | 0 | 10100 |
| 30204 | 60061 | 30101 | 10101 | 20000 | 10101 | 20002 | 35249 | 126915 | 30103 | 10201 | 20003 | 10201 | 40005 | 0 | 10001 | 20000 | 0 | 10100 |
| 30204 | 60061 | 30101 | 10101 | 20000 | 10101 | 20002 | 35249 | 126835 | 30103 | 10201 | 20003 | 10201 | 40005 | 0 | 10001 | 20000 | 0 | 10100 |
| 30204 | 60064 | 30101 | 10101 | 20000 | 10101 | 20002 | 35249 | 126878 | 30103 | 10201 | 20003 | 10201 | 40005 | 0 | 10001 | 20000 | 0 | 10100 |
| 30204 | 60061 | 30101 | 10101 | 20000 | 10101 | 20002 | 35249 | 126817 | 30103 | 10201 | 20003 | 10201 | 40005 | 0 | 10001 | 20000 | 0 | 10100 |
Result (median cycles for code): 6.0057
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 30029 | 60746 | 30139 | 10052 | 20087 | 10052 | 20002 | 35069 | 127006 | 30013 | 10021 | 20003 | 10020 | 40000 | 10001 | 20000 | 10010 |
| 30024 | 60057 | 30011 | 10011 | 20000 | 10010 | 20000 | 35050 | 127004 | 30010 | 10020 | 20000 | 10020 | 40000 | 10001 | 20000 | 10010 |
| 30024 | 60057 | 30011 | 10011 | 20000 | 10010 | 20000 | 35050 | 126996 | 30010 | 10020 | 20000 | 10020 | 40000 | 10001 | 20000 | 10010 |
| 30024 | 60057 | 30011 | 10011 | 20000 | 10010 | 20000 | 35050 | 127016 | 30010 | 10020 | 20000 | 10020 | 40000 | 10001 | 20000 | 10010 |
| 30024 | 60057 | 30011 | 10011 | 20000 | 10010 | 20000 | 35050 | 127008 | 30010 | 10020 | 20000 | 10020 | 40000 | 10001 | 20000 | 10010 |
| 30025 | 60103 | 30047 | 10023 | 20024 | 10023 | 20000 | 35050 | 127004 | 30010 | 10020 | 20000 | 10020 | 40000 | 10001 | 20000 | 10010 |
| 30024 | 60064 | 30011 | 10011 | 20000 | 10010 | 20000 | 35050 | 126833 | 30010 | 10020 | 20000 | 10020 | 40000 | 10001 | 20000 | 10010 |
| 30024 | 60057 | 30011 | 10011 | 20000 | 10010 | 20000 | 35050 | 127000 | 30010 | 10020 | 20000 | 10020 | 40000 | 10001 | 20000 | 10010 |
| 30024 | 60057 | 30011 | 10011 | 20000 | 10010 | 20000 | 35050 | 127000 | 30010 | 10020 | 20000 | 10020 | 40000 | 10001 | 20000 | 10010 |
| 30024 | 60057 | 30011 | 10011 | 20000 | 10010 | 20000 | 35050 | 126959 | 30010 | 10020 | 20000 | 10020 | 40000 | 10001 | 20000 | 10010 |
Code:
swpal x0, x1, [x6]
mov x7, 8
(fused SUBS/B.cc loop)
Result (median cycles for code): 24.0046
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 20205 | 240147 | 20125 | 101 | 20024 | 100 | 20004 | 300 | 2365780 | 20104 | 200 | 20004 | 200 | 40008 | 1 | 20000 | 100 |
| 20205 | 240071 | 20125 | 101 | 20024 | 100 | 20004 | 300 | 2365802 | 20104 | 200 | 20004 | 200 | 40008 | 1 | 20000 | 100 |
| 20204 | 240045 | 20105 | 101 | 20004 | 100 | 20004 | 300 | 2365802 | 20104 | 200 | 20004 | 200 | 40008 | 1 | 20000 | 100 |
| 20204 | 240050 | 20105 | 101 | 20004 | 100 | 20004 | 300 | 2365802 | 20104 | 200 | 20004 | 200 | 40048 | 1 | 20000 | 100 |
| 20204 | 240044 | 20105 | 101 | 20004 | 100 | 20004 | 300 | 2365802 | 20104 | 200 | 20004 | 200 | 40008 | 1 | 20000 | 100 |
| 20204 | 240044 | 20105 | 101 | 20004 | 100 | 20004 | 300 | 2365802 | 20104 | 200 | 20004 | 200 | 40008 | 1 | 20000 | 100 |
| 20204 | 240044 | 20105 | 101 | 20004 | 100 | 20004 | 300 | 2365881 | 20104 | 200 | 20004 | 200 | 40008 | 1 | 20000 | 100 |
| 20204 | 240044 | 20105 | 101 | 20004 | 100 | 20004 | 300 | 2365802 | 20104 | 200 | 20004 | 200 | 40008 | 1 | 20000 | 100 |
| 20204 | 240044 | 20105 | 101 | 20004 | 100 | 20024 | 300 | 2366309 | 20124 | 200 | 20024 | 200 | 40048 | 1 | 20000 | 100 |
| 20204 | 240044 | 20105 | 101 | 20004 | 100 | 20004 | 300 | 2365822 | 20104 | 200 | 20004 | 200 | 40008 | 1 | 20000 | 100 |
Result (median cycles for code): 24.0039
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 20025 | 240144 | 20034 | 11 | 20023 | 10 | 20000 | 30 | 2362738 | 20010 | 20 | 20000 | 20 | 40000 | 1 | 20000 | 10 |
| 20024 | 240046 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 2362644 | 20010 | 20 | 20000 | 20 | 40000 | 1 | 20000 | 10 |
| 20024 | 240039 | 20011 | 11 | 20000 | 10 | 20044 | 30 | 2363450 | 20054 | 20 | 20044 | 20 | 40000 | 1 | 20000 | 10 |
| 20024 | 240039 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 2362644 | 20010 | 20 | 20000 | 20 | 40000 | 1 | 20000 | 10 |
| 20024 | 240039 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 2362707 | 20010 | 20 | 20000 | 20 | 40052 | 1 | 20000 | 10 |
| 20024 | 240041 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 2362644 | 20010 | 20 | 20000 | 20 | 40000 | 1 | 20000 | 10 |
| 20024 | 240039 | 20011 | 11 | 20000 | 10 | 20024 | 30 | 2363169 | 20034 | 20 | 20024 | 20 | 40000 | 1 | 20000 | 10 |
| 20024 | 240039 | 20011 | 11 | 20000 | 10 | 20044 | 30 | 2363219 | 20054 | 20 | 20044 | 20 | 40000 | 1 | 20000 | 10 |
| 20025 | 240088 | 20035 | 11 | 20024 | 10 | 20000 | 30 | 2362644 | 20010 | 20 | 20000 | 20 | 40000 | 1 | 20000 | 10 |
| 20024 | 240039 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 2362644 | 20010 | 20 | 20000 | 20 | 40000 | 1 | 20000 | 10 |