Icestorm: STR (post-index, 64-bit) measurements

Code:

  str x0, [x6], #8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	1411	2059	1041	1018	1040	1000	4641	18325	2000	1000	2000	1001	1000
1004	1074	2001	1001	1000	1000	1000	4641	17479	2000	1000	2000	1001	1000
1004	1074	2001	1001	1000	1000	1000	4641	17497	2000	1000	2000	1001	1000
1004	1077	2001	1001	1000	1000	1000	4641	17569	2000	1000	2000	1001	1000
1004	1107	2001	1001	1000	1000	1000	4641	17623	2000	1000	2000	1001	1000
1004	1078	2001	1001	1000	1000	1000	4641	17569	2000	1000	2000	1001	1000
1004	1077	2001	1001	1000	1000	1000	4641	18217	2000	1000	2000	1001	1000
1004	1080	2001	1001	1000	1000	1000	4641	17641	2000	1000	2000	1001	1000
1004	1077	2001	1001	1000	1000	1000	4641	17695	2000	1000	2000	1001	1000
1004	1076	2001	1001	1000	1000	1000	4629	18937	2000	1000	2000	1001	1000

Test 2: Latency 2->2

Code:

  str x0, [x6], #8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0089

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10209	11206	20400	10310	10090	10310	10003	105464	171163	20109	200	10010	200	20020	10001	10000	100
10204	10088	20104	10104	10000	10104	10002	43508	170881	20106	200	10008	200	20016	10004	10000	100
10204	10090	20104	10104	10000	10104	10002	43510	170809	20106	200	10008	200	20016	10004	10000	100
10204	10091	20104	10104	10000	10104	10002	43510	170935	20106	200	10008	200	20016	10003	10000	100
10204	10088	20104	10104	10000	10104	10002	43509	170863	20106	200	10008	200	20016	10003	10000	100
10204	10088	20104	10104	10000	10104	10002	43511	170899	20106	200	10008	200	20016	10004	10000	100
10204	10086	20104	10104	10000	10104	10002	43510	170827	20106	200	10008	200	20016	10004	10000	100
10204	10088	20104	10104	10000	10104	10002	43511	170845	20106	200	10008	200	20016	10004	10000	100
10204	10099	20104	10104	10000	10104	10002	43516	171511	20106	200	10008	200	20016	10004	10000	100
10204	10089	20104	10104	10000	10104	10002	43510	170809	20106	200	10008	200	20016	10004	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0094

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10030	12006	20353	10246	10107	10250	10002	60820	170904	20016	20	10008	20	20000	10001	10000	10
10025	10225	20064	10047	10017	10052	10000	60522	171078	20010	20	10000	20	20000	10001	10000	10
10024	10105	20011	10011	10000	10010	10000	43071	171199	20010	20	10000	20	20000	10001	10000	10
10024	10103	20011	10011	10000	10010	10000	43069	170839	20010	20	10000	20	20000	10001	10000	10
10024	10130	20011	10011	10000	10010	10000	43078	171337	20010	20	10000	20	20000	10001	10000	10
10024	10111	20011	10011	10000	10010	10000	43074	171307	20010	20	10000	20	20000	10001	10000	10
10024	10098	20011	10011	10000	10010	10000	43075	170941	20010	20	10000	20	20000	10001	10000	10
10024	10108	20011	10011	10000	10010	10000	43071	170929	20010	20	10000	20	20000	10001	10000	10
10024	10094	20011	10011	10000	10010	10000	43071	170875	20010	20	10000	20	20000	10001	10000	10
10024	10094	20011	10011	10000	10010	10000	43071	170929	20010	20	10000	20	20000	10001	10000	10

Test 3: throughput

Count: 8

Code:

  str x0, [x6], #8
  str x0, [x7], #8
  str x0, [x8], #8
  str x0, [x9], #8
  str x0, [x10], #8
  str x0, [x11], #8
  str x0, [x12], #8
  str x0, [x13], #8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80209	81115	160401	80311	80090	80311	80002	240312	1360162	160106	200	80008	200	160016	80005	80000	100
80204	80056	160105	80105	80000	80104	80002	240312	1360051	160106	200	80008	200	160016	80005	80000	100
80204	80048	160105	80105	80000	80104	80002	240312	1360051	160106	200	80008	200	160016	80005	80000	100
80204	80048	160105	80105	80000	80104	80002	240312	1360051	160106	200	80008	200	160016	80005	80000	100
80204	80048	160105	80105	80000	80104	80002	240312	1360051	160106	200	80008	200	160016	80005	80000	100
80204	80048	160105	80105	80000	80104	80002	240312	1360051	160106	200	80008	200	160016	80005	80000	100
80204	80048	160105	80105	80000	80104	80002	240312	1360051	160106	200	80008	200	160016	80005	80000	100
80204	80048	160105	80105	80000	80104	80002	240312	1360051	160106	200	80008	200	160016	80005	80000	100
80204	80048	160105	80105	80000	80104	80002	240312	1360051	160106	200	80008	200	160016	80005	80000	100
80205	80107	160154	80137	80017	80140	80002	240312	1360211	160106	200	80008	200	160016	80005	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80029	81493	160305	80215	80090	80214	80002	240042	1360051	160016	20	80008	20	160176	80085	80000	10
80024	80048	160015	80015	80000	80014	80000	240030	1360045	160010	20	80000	20	160000	80001	80000	10
80024	80048	160011	80011	80000	80010	80000	240030	1360045	160010	20	80000	20	160000	80001	80000	10
80024	80048	160011	80011	80000	80010	80000	240030	1360045	160010	20	80000	20	160000	80001	80000	10
80024	80048	160011	80011	80000	80010	80000	240030	1360045	160010	20	80000	20	160000	80001	80000	10
80024	80048	160011	80011	80000	80010	80000	240030	1360045	160010	20	80000	20	160000	80001	80000	10
80024	80048	160011	80011	80000	80010	80000	240030	1360171	160010	20	80000	20	160000	80001	80000	10
80024	80048	160011	80011	80000	80010	80000	240030	1360045	160010	20	80000	20	160000	80001	80000	10
80024	80048	160011	80011	80000	80010	80000	240030	1360045	160010	20	80000	20	160000	80001	80000	10
80024	80048	160011	80011	80000	80010	80035	240149	1360647	160085	20	80048	20	160000	80001	80000	10

STR (post-index, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 2->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations