Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

PRFM (register, PLIL1KEEP)

Test 1: uops

Code:

  prfm plil1keep, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1004	2059	1001	1	1000	1000	34136	1000	1000	1000	1	1000
1004	2058	1001	1	1000	1000	34136	1000	1000	1000	1	1000
1004	2058	1001	1	1000	1000	34136	1000	1000	1000	1	1000
1004	2058	1001	1	1000	1000	34136	1000	1000	1000	1	1000
1004	2058	1001	1	1000	1000	34136	1000	1000	1000	1	1000
1004	2058	1001	1	1000	1000	34136	1000	1000	1000	1	1000
1004	2058	1001	1	1000	1000	34136	1000	1000	1000	1	1000
1004	2058	1001	1	1000	1000	34136	1000	1000	1000	1	1000
1004	2058	1001	1	1000	1000	34136	1000	1000	1000	1	1000
1004	2058	1001	1	1000	1000	35270	1000	1000	1000	1	1000

Test 2: throughput

Code:

  prfm plil1keep, [x6]
  add x6, x6, 64

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20204	20361	20228	10168	10060	10171	10000	61697	347130	20103	10205	10005	10213	10013	10006	10000	10100
20204	20073	20105	10105	10000	10108	10000	61565	347109	20103	10205	10005	10212	10012	10005	10000	10100
20204	20028	20102	10102	10000	10104	10004	61394	348781	20114	10212	10012	10202	10002	10001	10000	10100
20204	20049	20105	10105	10000	10110	10004	61394	348727	20114	10212	10012	10212	10012	10005	10000	10100
20204	19980	20101	10101	10000	10100	10000	61398	347537	20100	10202	10002	10210	10010	10005	10000	10100
20204	20009	20105	10105	10000	10110	10000	61656	347181	20104	10206	10006	10212	10012	10005	10000	10100
20204	20023	20105	10105	10000	10110	10000	61588	347321	20100	10202	10002	10212	10012	10005	10000	10100
20204	19964	20105	10105	10000	10110	10004	61394	348745	20114	10212	10012	10202	10002	10001	10000	10100
20204	19978	20101	10101	10000	10100	10000	61730	346625	20102	10204	10004	10210	10010	10003	10000	10100
20204	19918	20103	10103	10000	10108	10006	61141	347855	20118	10214	10014	10210	10010	10005	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0131

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20024	23907	20011	10011	10000	10012	10004	61119	350635	20023	10031	10011	10020	10000	10001	10000	10010
20024	20131	20011	10011	10000	10010	10000	60992	350701	20010	10020	10000	10020	10000	10001	10000	10010
20024	20131	20011	10011	10000	10010	10000	60992	350701	20010	10020	10000	10020	10000	10001	10000	10010
20024	20131	20011	10011	10000	10010	10000	60992	350701	20010	10020	10000	10020	10000	10001	10000	10010
20024	20131	20011	10011	10000	10010	10000	60992	350701	20010	10020	10000	10020	10000	10001	10000	10010
20024	20131	20011	10011	10000	10010	10000	60992	350701	20010	10020	10000	10020	10000	10001	10000	10010
20024	20131	20011	10011	10000	10010	10000	60992	350701	20010	10020	10000	10020	10000	10001	10000	10010
20024	20131	20011	10011	10000	10010	10000	60992	350701	20010	10020	10000	10020	10000	10001	10000	10010
20024	20131	20011	10011	10000	10010	10000	60992	350701	20010	10020	10000	10020	10000	10001	10000	10010
20024	20131	20011	10011	10000	10010	10000	60992	350701	20010	10020	10000	10020	10000	10001	10000	10010

Test 3: throughput

Code:

  prfm plil1keep, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0058

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10204	20058	10101	101	10000	100	10006	300	349012	10106	200	10012	200	10012	1	10000	100
10204	20058	10101	101	10000	100	10006	300	349160	10106	200	10012	200	10012	1	10000	100
10204	20058	10101	101	10000	100	10006	300	349160	10106	200	10012	200	10012	1	10000	100
10204	20058	10101	101	10000	100	10006	300	349160	10106	200	10012	200	10012	1	10000	100
10204	20058	10101	101	10000	100	10006	300	349160	10106	200	10012	200	10012	1	10000	100
10204	20058	10101	101	10000	100	10006	300	349160	10106	200	10012	200	10012	1	10000	100
10204	20058	10101	101	10000	100	10006	300	349160	10106	200	10012	200	10012	1	10000	100
10204	20058	10101	101	10000	100	10006	300	349160	10106	200	10012	200	10012	1	10000	100
10204	20058	10101	101	10000	100	10006	300	349160	10106	200	10012	200	10012	1	10000	100
10204	20058	10101	101	10000	100	10006	300	349160	10106	200	10012	200	10012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0958

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10024	20049	10011	11	10000	10	10006	30	349222	10016	20	10012	20	10000	1	10000	10
10024	20048	10011	11	10000	10	10000	30	349214	10010	20	10000	20	10000	1	10000	10
10024	20048	10011	11	10000	10	10000	30	349214	10010	20	10000	20	10000	1	10000	10
10024	20075	10011	11	10000	10	10000	30	349360	10010	20	10000	20	10000	1	10000	10
10024	20122	10011	11	10000	10	10000	30	350082	10010	20	10000	20	10000	1	10000	10
10024	20103	10011	11	10000	10	10000	30	349638	10010	20	10000	20	10000	1	10000	10
10024	20266	10041	11	10030	10	10000	30	360786	10010	20	10006	20	10000	1	10000	10
10024	20751	10011	11	10000	10	10000	30	362524	10010	20	10000	20	10000	1	10000	10
10024	20833	10011	11	10000	10	10000	30	363238	10010	20	10000	20	10000	1	10000	10
10024	20748	10011	11	10000	10	10096	30	366998	10106	20	10114	20	10000	1	10000	10