Icestorm: CMN (uxtw, 32-bit) measurements

Code:

  cmn w0, w1, uxtw

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)
1004	517	1001	1001	1000	3000	1000	1000	2000	1001
1004	393	1001	1001	1000	3000	1000	1000	2000	1001
1004	392	1001	1001	1000	3000	1000	1000	2000	1001
1004	391	1001	1001	1000	3000	1000	1000	2000	1001
1004	393	1001	1001	1000	3000	1000	1000	2000	1001
1004	390	1001	1001	1000	3000	1000	1000	2000	1001
1004	392	1001	1001	1000	3000	1000	1000	2000	1001
1004	391	1001	1001	1000	3000	1000	1000	2000	1001
1004	395	1001	1001	1000	3000	1000	1000	2000	1001
1004	391	1001	1001	1000	3000	1000	1000	2000	1001

Test 2: Latency 3->1

Chain cycles: 1

Code:

  cmn w0, w1, uxtw
  cset x0, cc

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20107	0	519338	0	20108	20214	0	30221	20001	10100
20204	20030	20101	20101	20108	0	519548	0	20108	20216	0	30224	20001	10100
20204	20030	20101	20101	20108	0	519548	0	20108	20216	0	30224	20001	10100
20205	20060	20115	20115	20147	0	519443	0	20108	20216	0	30224	20001	10100
20204	20030	20101	20101	20108	0	519548	0	20108	20216	0	30224	20001	10100
20204	20030	20101	20101	20108	0	519548	0	20108	20216	0	30224	20001	10100
20204	20030	20101	20101	20108	0	519548	0	20108	20216	0	30224	20001	10100
20204	20030	20101	20101	20108	0	519548	0	20108	20216	0	30224	20001	10100
20204	20030	20101	20101	20108	0	519548	0	20108	20216	0	30224	20001	10100
20204	20030	20101	20101	20108	0	519548	0	20108	20216	0	30224	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519496	20018	20034	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010

Test 3: Latency 3->2

Chain cycles: 1

Code:

  cmn w0, w1, uxtw
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20107	519464	20110	20218	30224	20001	10100
20204	20030	20101	20101	20107	519435	20107	20214	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519638	20018	20036	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519956	20058	20084	30020	20001	10010
20024	20030	20011	20011	20010	519916	20050	20068	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30158	20043	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30092	20022	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010

Test 4: throughput

Count: 8

Code:

  cmn w0, w1, uxtw
  cmn w0, w1, uxtw
  cmn w0, w1, uxtw
  cmn w0, w1, uxtw
  cmn w0, w1, uxtw
  cmn w0, w1, uxtw
  cmn w0, w1, uxtw
  cmn w0, w1, uxtw

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3634

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	29274	80114	80114	80119	240351	80117	80218	160236	80014	100
80204	28992	80113	80113	80117	240360	80120	80220	160240	80013	100
80204	29056	80113	80113	80118	240360	80120	80220	160240	80012	100
80204	29157	80113	80113	80118	240354	80118	80220	160240	80015	100
80204	29049	80113	80113	80118	240354	80118	80220	160240	80013	100
80204	29113	80114	80114	80119	240351	80117	80220	160240	80015	100
80204	29060	80115	80115	80120	240351	80117	80220	160240	80015	100
80204	29123	80113	80113	80118	240360	80120	80220	160240	80015	100
80204	29058	80115	80115	80120	240360	80120	80220	160240	80013	100
80204	29128	80115	80115	80120	240354	80118	80220	160240	80015	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3631

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	30195	80034	80034	80038	240142	80040	80042	160020	80011	10
80024	29022	80021	80021	80020	240127	80020	80020	160020	80011	10
80025	29155	80073	80073	80078	240118	80020	80020	160020	80011	10
80024	29082	80021	80021	80020	240118	80020	80020	160020	80011	10
80024	29098	80021	80021	80020	240113	80020	80020	160020	80011	10
80024	29006	80021	80021	80020	240103	80020	80020	160020	80011	10
80024	29106	80021	80021	80020	240109	80020	80020	160020	80011	10
80024	28996	80021	80021	80020	240113	80020	80020	160020	80011	10
80024	29106	80021	80021	80020	240101	80020	80020	160020	80011	10
80024	28990	80021	80021	80020	240106	80020	80020	160020	80011	10

CMN (uxtw, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 3->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations