Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDRSH (64-bit)

Test 1: uops

Code:

  ldrsh x0, [x6]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	644	1021	1	1020	1000	8166	1000	1000	1000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	1000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	1000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	1000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	1000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	1000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	1000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	1000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	1000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	1000	1	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh x0, [x6]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70297	40108	30107	10001	30130	10003	1859485	693973	40106	30212	10004	60224	10004	30003	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	10004	30002	10000	30100
40205	70162	40110	30108	10002	30135	10003	1859608	694081	40106	30212	10004	60224	10004	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	10004	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	10004	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60302	10017	30009	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	10004	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	10004	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	10004	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	10004	30002	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70172	40018	30017	10001	30040	10003	1859671	694738	40016	30032	10004	60020	10000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60098	10013	30009	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	30003	10000	30010
40024	70050	40013	30013	10000	30010	10003	1859806	694791	40016	30032	10004	60020	10000	30002	10000	30010

Test 3: throughput

Count: 8

Code:

  ldrsh x0, [x6]
  ldrsh x0, [x6]
  ldrsh x0, [x6]
  ldrsh x0, [x6]
  ldrsh x0, [x6]
  ldrsh x0, [x6]
  ldrsh x0, [x6]
  ldrsh x0, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40169	80127	101	80026	100	80008	300	280262	80108	200	80012	200	80012	1	80000	100
80205	40112	80131	101	80030	100	80008	300	641978	80108	200	80012	200	80012	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	80012	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	80012	1	80000	100
80204	40068	80101	101	80000	100	80008	300	640268	80108	200	80012	200	80012	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	80012	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	80012	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	80012	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	80012	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	80012	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40207	80037	11	80026	10	80008	30	400190	0	80018	20	80012	0	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	0	80010	20	80000	0	20	80000	1	80000	10
80024	40062	80011	11	80000	10	80000	30	640220	0	80010	20	80000	0	20	80000	1	80000	10
80024	40056	80011	11	80000	10	80000	30	640220	0	80010	20	80000	0	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	0	80010	20	80000	0	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	0	80010	20	80000	0	20	80000	1	80000	10
80024	40062	80011	11	80000	10	80000	30	640220	0	80010	20	80000	0	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	0	80010	20	80000	0	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	0	80010	20	80000	0	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80059	30	446289	0	80069	20	80071	0	20	80072	1	80000	10