Icestorm: LDRSW (post-index) measurements

Code:

  ldrsw x0, [x6], #8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
2005	1264	2035	1020	1015	1038	1000	21007	17796	2000	1000	1000	1000	1000	1001	1000	1000
2004	1076	2001	1001	1000	1000	1000	21039	17540	2000	1000	1000	1000	1000	1001	1000	1000
2004	1072	2001	1001	1000	1000	1000	20744	17477	2000	1000	1000	1000	1000	1001	1000	1000
2004	1126	2001	1001	1000	1000	1000	21236	17743	2000	1000	1000	1000	1000	1001	1000	1000
2004	1060	2001	1001	1000	1000	1000	21174	17555	2000	1000	1000	1000	1000	1001	1000	1000
2004	1074	2001	1001	1000	1000	1000	21236	17558	2000	1000	1000	1000	1000	1001	1000	1000
2004	1079	2001	1001	1000	1000	1000	21175	17600	2000	1000	1000	1000	1000	1001	1000	1000
2004	1088	2001	1001	1000	1000	1000	21162	17648	2000	1000	1000	1000	1000	1001	1000	1000
2004	1074	2001	1001	1000	1000	1000	21404	17611	2000	1000	1000	1000	1000	1001	1000	1000
2004	1100	2001	1001	1000	1000	1000	21297	17556	2000	1000	1000	1000	1000	1001	1000	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsw x0, [x6], #8
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0123

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50209	71218	50160	40155	10005	40247	10003	1850820	534896	50109	40212	10004	70221	10004	40009	10000	40100
50204	70211	50109	40109	10000	40106	10003	1852467	535329	50109	40212	10004	70292	10015	40025	10000	40100
50204	70205	50109	40109	10000	40106	10003	1853871	535735	50109	40212	10004	70221	10004	40009	10000	40100
50204	70232	50109	40109	10000	40106	10003	1853790	535793	50109	40212	10004	70221	10004	40004	10000	40100
50204	70105	50104	40104	10000	40106	10003	1850388	534746	50109	40212	10004	70221	10004	40004	10000	40100
50204	70107	50104	40104	10000	40106	10003	1850388	534746	50109	40212	10004	70221	10004	40004	10000	40100
50204	70107	50104	40104	10000	40106	10003	1850388	534746	50109	40212	10004	70221	10004	40004	10000	40100
50205	70191	50117	40115	10002	40140	10003	1850523	534781	50109	40212	10004	70221	10004	40004	10000	40100
50204	70107	50104	40104	10000	40106	10003	1850388	534746	50109	40212	10004	70221	10004	40004	10000	40100
50204	70107	50104	40104	10000	40106	10003	1850388	534746	50109	40212	10004	70221	10004	40004	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0115

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50029	71241	50070	40065	10005	40156	10003	1850748	535202	50019	40032	10004	70020	10000	40004	10000	40010
50024	70115	50014	40014	10000	40010	10000	1850606	535137	50010	40020	10000	70109	10013	40015	10000	40010
50024	70111	50014	40014	10000	40010	10000	1852199	535642	50010	40020	10000	70041	10004	40005	10000	40010
50024	70115	50014	40014	10000	40010	10000	1850660	535151	50010	40020	10000	70020	10000	40004	10000	40010
50024	70115	50014	40014	10000	40010	10000	1850660	535151	50010	40020	10000	70020	10000	40004	10000	40010
50024	70115	50014	40014	10000	40010	10000	1850660	535151	50010	40020	10000	70020	10000	40004	10000	40010
50024	70115	50014	40014	10000	40010	10000	1850660	535151	50010	40020	10000	70020	10000	40004	10000	40010
50024	70115	50014	40014	10000	40010	10000	1850660	535151	50010	40020	10000	70020	10000	40004	10000	40010
50024	70115	50014	40014	10000	40010	10000	1850660	535151	50010	40020	10000	70020	10000	40004	10000	40010
50024	70115	50014	40014	10000	40010	10012	1854721	536356	50059	40071	10013	70020	10000	40004	10000	40010

Test 3: throughput

Count: 8

Code:

  ldrsw x0, [x6], #8
  ldrsw x0, [x7], #8
  ldrsw x0, [x8], #8
  ldrsw x0, [x9], #8
  ldrsw x0, [x10], #8
  ldrsw x0, [x11], #8
  ldrsw x0, [x12], #8
  ldrsw x0, [x13], #8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5404

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160209	44220	160423	80313	0	80110	80316	0	80011	240613	644480	160124	80213	80013	80212	80012	80009	80000	80100
160204	43236	160109	80109	0	80000	80112	0	80054	240991	616846	160208	80254	80054	80212	80012	80009	80000	80100
160204	43235	160109	80109	0	80000	80112	0	80011	240610	645660	160123	80212	80012	80208	80008	80007	80000	80100
160205	43303	160184	80151	0	80033	80154	0	80012	240658	644309	160124	80212	80012	80212	80012	80009	80000	80100
160204	43231	160109	80109	0	80000	80112	0	80012	240610	640183	160124	80212	80012	80212	80012	80009	80000	80100
160204	43232	160109	80109	0	80000	80112	0	80012	240610	644178	160124	80212	80012	80212	80012	80009	80000	80100
160204	43231	160109	80109	0	80000	80112	0	80012	240610	643781	160124	80212	80012	80210	80010	80007	80000	80100
162913	58998	162704	81778	5	80921	81642	6	80012	240613	642194	160125	80213	80013	80212	80012	80009	80000	80100
160204	43236	160110	80109	0	80001	80112	0	80010	240610	638811	160122	80212	80012	80212	80012	80009	80000	80100
160204	43233	160109	80109	0	80000	80112	0	80010	240610	642915	160122	80212	80012	80212	80012	80009	80000	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5404

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160029	44375	160332	80223	80109	80226	80053	240706	603468	160116	80073	80053	80033	80013	80010	80000	80010
160024	43244	160011	80011	80000	80010	80000	240304	647600	160010	80020	80000	80020	80000	80001	80000	80010
160024	43230	160011	80011	80000	80010	80000	240304	643490	160010	80020	80000	80020	80000	80001	80000	80010
160024	43230	160011	80011	80000	80010	80000	240304	645136	160010	80020	80000	80020	80000	80001	80000	80010
160024	43230	160011	80011	80000	80010	80000	240304	643778	160010	80020	80000	80020	80000	80001	80000	80010
160024	43231	160011	80011	80000	80010	80000	240304	646435	160010	80020	80000	80020	80000	80001	80000	80010
160024	43228	160011	80011	80000	80010	80000	240304	642603	160010	80020	80000	80020	80000	80001	80000	80010
160024	43228	160011	80011	80000	80010	80000	240304	646652	160010	80020	80000	80020	80000	80001	80000	80010
160024	43228	160011	80011	80000	80010	80000	240304	641522	160010	80020	80000	80020	80000	80001	80000	80010
160024	43228	160011	80011	80000	80010	80000	240304	642791	160010	80020	80000	80020	80000	80001	80000	80010

LDRSW (post-index)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations