Icestorm: SDIV (fast, 32-bit) measurements

Code:

  sdiv w0, w1, w2

Initialization

  mov w1, #0
  mov w2, #0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	7030	2001	2001	1000	61748	1000	1000	2000	2001	1000
1004	7030	2001	2001	1000	61748	1000	1000	2000	2001	1000
1004	7030	2001	2001	1000	61748	1000	1000	2000	2001	1000
1004	7030	2001	2001	1000	61748	1000	1000	2000	2001	1000
1004	7030	2001	2001	1000	61748	1000	1000	2000	2001	1000
1004	7030	2001	2001	1000	61748	1000	1000	2000	2001	1000
1004	7030	2001	2001	1000	61748	1000	1000	2000	2001	1000
1004	7030	2001	2001	1000	61748	1000	1000	2000	2001	1000
1004	7030	2001	2001	1000	61748	1000	1000	2000	2001	1000
1004	7030	2001	2001	1000	61748	1000	1000	2000	2001	1000

Test 2: Latency 1->2

Chain cycles: 2

Code:

  sdiv w0, w1, w2
  eor x1, x1, x0
  eor x1, x1, x0

Initialization

  mov w1, #0
  mov w2, #0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 7.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
30204	90030	40201	40201	30203	2398634	30203	30210	60224	40101	30100
30204	90030	40201	40201	30203	2399019	30234	30248	60224	40101	30100
30204	90030	40201	40201	30203	2398718	30203	30212	60224	40101	30100
30204	90030	40201	40201	30203	2398718	30203	30212	60224	40101	30100
30204	90030	40201	40201	30203	2398718	30203	30212	60224	40101	30100
30204	90030	40201	40201	30203	2398718	30203	30212	60224	40101	30100
30204	90222	40242	40242	30330	2398718	30203	30212	60224	40101	30100
30204	90124	40220	40220	30266	2399048	30235	30252	60376	40120	30100
30204	90030	40201	40201	30203	2398718	30203	30212	60224	40101	30100
30204	90030	40201	40201	30203	2399710	30266	30290	60224	40101	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 7.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
30024	90030	40011	40011	30013	2398935	30010	30020	60020	40001	30010
30024	90030	40011	40011	30010	2398977	30010	30020	60020	40001	30010
30024	90030	40011	40011	30010	2398977	30010	30020	60020	40001	30010
30024	90030	40011	40011	30010	2398977	30010	30020	60124	40006	30010
30024	90030	40011	40011	30010	2398977	30010	30020	60020	40001	30010
30025	90060	40016	40016	30043	2398977	30010	30020	60020	40001	30010
30024	90030	40011	40011	30010	2398977	30010	30020	60020	40001	30010
30024	90030	40011	40011	30010	2398977	30010	30020	60020	40001	30010
30024	90030	40011	40011	30010	2398977	30010	30020	60020	40001	30010
30024	90030	40011	40011	30010	2398977	30010	30020	60020	40001	30010

Test 3: Latency 1->3

Chain cycles: 2

Code:

  sdiv w0, w1, w2
  eor x2, x2, x0
  eor x2, x2, x0

Initialization

  mov w1, #0
  mov w2, #0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 7.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
30204	90030	40201	40201	30203	2398677	30203	30210	60224	40101	30100
30204	90030	40201	40201	30203	2398718	30203	30212	60224	40101	30100
30204	90030	40201	40201	30203	2398718	30203	30212	60224	40101	30100
30204	90030	40201	40201	30203	2398718	30203	30212	60224	40101	30100
30204	90030	40201	40201	30203	2399075	30233	30251	60224	40101	30100
30204	90030	40201	40201	30203	2398718	30203	30212	60224	40101	30100
30204	90030	40201	40201	30203	2398718	30203	30212	60224	40101	30100
30204	90030	40201	40201	30203	2398718	30203	30212	60224	40101	30100
30204	90030	40201	40201	30203	2398718	30203	30212	60224	40101	30100
30204	90030	40201	40201	30203	2398718	30203	30212	60224	40101	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 7.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
30024	90030	40011	40011	0	30013	2398935	30010	30020	60020	40001	30010
30024	90030	40011	40011	0	30010	2398977	30010	30020	60020	40001	30010
30024	90030	40011	40011	0	30010	2398977	30010	30020	60020	40001	30010
30024	90030	40011	40011	0	30010	2398977	30010	30020	60020	40001	30010
30024	90030	40011	40011	0	30010	2399338	30044	30072	60020	40001	30010
30024	90030	40011	40011	0	30010	2398977	30010	30020	60020	40001	30010
30024	90030	40011	40011	0	30010	2398977	30010	30020	60020	40001	30010
30024	90030	40011	40011	0	30010	2398977	30010	30020	60020	40001	30010
30024	90030	40011	40011	0	30010	2398977	30010	30020	60020	40001	30010
30024	90030	40011	40011	0	30010	2398977	30010	30020	60020	40001	30010

Test 4: throughput

Code:

  sdiv w0, w1, w2

Initialization

  mov w1, #0
  mov w2, #0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	70030	20101	20101	10100	620048	10100	10206	20212	20001	10100
10205	70060	20107	20107	10112	620048	10100	10206	20216	20001	10100
10204	70030	20101	20101	10100	620048	10100	10208	20216	20001	10100
10204	70030	20101	20101	10100	620048	10100	10208	20216	20001	10100
10204	70030	20101	20101	10100	620048	10100	10208	20216	20001	10100
10204	70030	20101	20101	10100	620048	10100	10208	20216	20001	10100
10204	70030	20101	20101	10100	620048	10100	10208	20216	20001	10100
10204	70030	20101	20101	10100	620048	10100	10208	20216	20001	10100
10204	70030	20101	20101	10100	620048	10100	10208	20216	20001	10100
10205	70060	20105	20105	10110	620048	10100	10208	20216	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	70030	20021	20021	10020	619808	10020	10020	20020	20011	10010
10024	70030	20021	20021	10020	619808	10020	10020	20020	20011	10010
10024	70030	20021	20021	10020	619808	10020	10020	20020	20011	10010
10024	70030	20021	20021	10020	619808	10020	10020	20020	20011	10010
10024	70030	20021	20021	10020	619808	10020	10020	20020	20011	10010
10024	70030	20021	20021	10020	619808	10020	10020	20020	20011	10010
10024	70030	20021	20021	10020	619808	10020	10020	20020	20011	10010
10024	70030	20021	20021	10020	619808	10020	10020	20020	20011	10010
10024	70030	20021	20021	10020	619808	10020	10020	20074	20016	10010
10024	70030	20021	20021	10020	619808	10020	10020	20020	20011	10010

SDIV (fast, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations