Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

STLXRB

Test 1: uops

Code:

  stlxrb w0, w1, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	3160	1019	1	1018	1000	51855	1000	1000	2000	1	1000
1004	3047	1001	1	1000	1000	51713	1000	1000	2000	1	1000
1004	3040	1001	1	1000	1000	51713	1000	1000	2000	1	1000
1004	3040	1001	1	1000	1000	51713	1000	1000	2000	1	1000
1004	3040	1001	1	1000	1000	51713	1000	1000	2000	1	1000
1004	3040	1001	1	1000	1000	51713	1000	1000	2000	1	1000
1004	3040	1001	1	1000	1000	51713	1000	1000	2000	1	1000
1004	3040	1001	1	1000	1000	51713	1000	1000	2000	1	1000
1004	3040	1001	1	1000	1000	51713	1000	1000	2000	1	1000
1004	3040	1001	1	1000	1000	51713	1000	1000	2000	1	1000

Test 2: throughput

Code:

  stlxrb w0, w1, [x6]
  add x6, x6, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0424

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20206	30681	20194	10158	10036	10157	10003	35477	339277	20106	10203	10003	10203	20006	10004	10000	10100
20204	30440	20104	10104	10000	10103	10003	35477	339221	20106	10203	10003	10232	20064	10033	10000	10100
20204	30414	20103	10103	10000	10102	10002	35463	339902	20103	10201	10002	10203	20006	10004	10000	10100
20204	30454	20103	10103	10000	10102	10002	35491	339140	20104	10202	10002	10202	20004	10003	10000	10100
20204	30416	20103	10103	10000	10102	10002	35491	339405	20104	10202	10002	10232	20064	10033	10000	10100
20204	30462	20103	10103	10000	10102	10002	35491	339025	20104	10202	10002	10202	20004	10003	10000	10100
20204	30429	20103	10103	10000	10102	10002	35491	339179	20104	10202	10002	10202	20004	10003	10000	10100
20204	30403	20103	10103	10000	10102	10002	35491	339222	20104	10202	10002	10202	20004	10003	10000	10100
20204	30417	20103	10103	10000	10102	10002	35491	339163	20104	10202	10002	10202	20004	10003	10000	10100
20204	30428	20103	10103	10000	10102	10002	35491	339193	20104	10202	10002	10202	20004	10003	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0442

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20026	30704	20102	10066	10036	10065	10002	35266	340175	20014	10022	10002	10085	20128	10064	10000	10010
20024	30465	20012	10012	10000	10011	10000	35259	339346	20010	10020	10000	10020	20000	10001	10000	10010
20027	30541	20112	10076	10036	10075	10000	35259	339713	20010	10020	10000	10020	20000	10001	10000	10010
20024	30436	20011	10011	10000	10010	10000	35259	339341	20010	10020	10000	10054	20066	10035	10000	10010
20024	30434	20011	10011	10000	10010	10000	35259	339419	20010	10020	10000	10020	20000	10001	10000	10010
20024	30457	20011	10011	10000	10010	10000	35259	339119	20010	10020	10000	10020	20000	10001	10000	10010
20024	30430	20011	10011	10000	10010	10000	35259	339337	20010	10020	10000	10051	20060	10032	10000	10010
20024	30433	20011	10011	10000	10010	10000	35259	339448	20010	10020	10000	10020	20000	10001	10000	10010
20025	30504	20061	10043	10018	10044	10000	35259	339595	20010	10020	10000	10020	20000	10001	10000	10010
20024	30434	20011	10011	10000	10010	10062	35936	341382	20134	10082	10062	10020	20000	10001	10000	10010

Test 3: throughput

Code:

  stlxrb w0, w1, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10205	30201	10119	101	10018	100	10000	300	528713	10100	200	10004	200	20008	1	10000	100
10204	30040	10101	101	10000	100	10000	300	528713	10100	200	10004	200	20008	1	10000	100
10204	30040	10101	101	10000	100	10000	300	528713	10100	200	10004	200	20008	1	10000	100
10204	30040	10101	101	10000	100	10000	300	528713	10100	200	10004	200	20008	1	10000	100
10204	30040	10101	101	10000	100	10000	300	528713	10100	200	10004	200	20008	1	10000	100
10204	30040	10101	101	10000	100	10000	300	528713	10100	200	10004	200	20008	1	10000	100
10204	30040	10101	101	10000	100	10000	300	528713	10100	200	10004	200	20008	1	10000	100
10204	30040	10101	101	10000	100	10000	300	528713	10100	200	10004	200	20008	1	10000	100
10204	30040	10101	101	10000	100	10000	300	528713	10100	200	10004	200	20008	1	10000	100
10204	30090	10101	101	10000	100	10000	300	528857	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10025	30284	10029	11	10018	10	10000	30	529755	10010	20	10004	20	20008	1	10000	10
10024	30044	10011	11	10000	10	10000	30	529415	10010	20	10000	20	20352	1	10000	10
10024	30068	10011	11	10000	10	10000	30	528713	10010	20	10000	20	20000	1	10000	10
10024	30040	10011	11	10000	10	10000	30	528713	10010	20	10000	20	20000	1	10000	10
10024	30040	10011	11	10000	10	10000	30	528713	10010	20	10000	20	20000	1	10000	10
10024	30040	10011	11	10000	10	10000	30	528839	10010	20	10000	20	20000	1	10000	10
10024	30068	10011	11	10000	10	10144	30	533645	10154	20	10176	20	20000	1	10000	10
10024	30040	10011	11	10000	10	10000	30	528713	10010	20	10000	20	20000	1	10000	10
10024	30040	10011	11	10000	10	10000	30	528713	10010	20	10000	20	20000	1	10000	10
10024	30040	10011	11	10000	10	10000	30	528713	10010	20	10000	20	20096	1	10000	10