Icestorm: LDRSH (register, 64-bit) measurements

Code:

  ldrsh x0, [x6, x7]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	789	1029	1	1028	1000	8238	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	2000	1	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh x0, [x6, x7]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70156	40108	30107	10001	30130	10003	1859539	693896	40106	30210	10004	60294	20034	30009	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100
40205	70072	40110	30108	10002	30135	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70158	40018	30017	10001	30040	10003	1859671	694738	40016	30032	10004	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1860246	694956	40010	30020	10000	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859841	694787	40010	30020	10000	60020	20000	30003	10000	30010
40024	70050	40013	30013	10000	30013	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1861731	695559	40010	30020	10000	60020	20000	30003	10000	30010
40024	70057	40013	30013	10000	30010	10000	1859733	694745	40010	30020	10000	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh x0, [x6, x7]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70150	40108	30107	10001	30130	10027	1862210	718079	40194	30287	10030	60220	20008	30003	10000	30100
40204	70050	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40205	70173	40111	30109	10002	30135	10003	1859824	694160	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70209	40018	30017	10001	30040	10003	1859779	694780	40016	30032	10004	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10016	1859852	698133	40061	30071	10018	60020	20000	30002	10000	30010
40024	70043	40012	30012	10000	30010	10004	1859671	729653	40017	30032	10005	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	20000	30002	10000	30010

Test 4: throughput

Count: 8

Code:

  ldrsh x0, [x6, x7]
  ldrsh x0, [x6, x7]
  ldrsh x0, [x6, x7]
  ldrsh x0, [x6, x7]
  ldrsh x0, [x6, x7]
  ldrsh x0, [x6, x7]
  ldrsh x0, [x6, x7]
  ldrsh x0, [x6, x7]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80206	40223	80164	101	80063	100	80008	300	272778	80108	200	80012	200	160028	1	80000	100
80204	40062	80101	101	80000	100	80008	300	640376	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160138	1	80000	100
80204	40163	80101	101	80000	100	80008	300	640502	80108	200	80012	200	160144	1	80000	100
80204	40150	80101	101	80000	100	80134	922	645028	80333	394	80152	200	160024	1	80000	100
80204	40063	80101	101	80000	100	80008	300	640520	80108	200	80012	200	160024	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40233	80037	11	80026	10	80000	30	640166	80010	20	80000	20	160000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640040	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	160000	1	80000	10
80024	40141	80011	11	80000	10	80000	30	640436	80010	20	80000	20	160000	1	80000	10
80024	40051	80011	11	80000	10	80000	30	640184	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80056	30	428134	80066	20	80069	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	160000	1	80000	10

LDRSH (register, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations